Patents by Inventor Yu-Ting Chung

Yu-Ting Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240110030
    Abstract: A styrene-modified polyethylene-based expandable resin particle is provided, which comprise a polyethylene resin and a polystyrene resin, wherein a content of the polyethylene resin ranges from 5 wt % to 30 wt % and a content of the polystyrene resin ranges from 70 wt % to 95 wt % based on 100 wt % of the polyethylene resin and the polystyrene resin, wherein the expandable resin particle comprises a xylene insoluble matter and an acetone insoluble matter, and a ratio of a content of the xylene insoluble matter to a content of the acetone insoluble matter ranges from 0.01 to 5. In addition, an expanded resin particle and a foamed resin molded article prepared by the aforesaid expandable resin particle are also provided. Furthermore, a method for manufacturing the aforesaid expandable resin particle is also provided.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 4, 2024
    Inventors: Han-Liou YI, Yao-Hsien CHUNG, Cheng-Ting HSIEH, Yu-Pin LIN, Keng-Wei HSU
  • Patent number: 11741871
    Abstract: Foldable displays may have portions folded into a folded configuration. Each folded portion may be observed by a user at a different viewing angle. As such, folding-artifacts may appear in the displayed image as a result of the different viewing angles. For example, a perceptible color difference and/or a perceptible brightness difference may appear between folded portions. Disclosed here are systems and methods to create compensated images that when displayed reduced the folding artifacts. The creation may include sensing a viewing angle for each portion and determining adjustments for pixels in each portion using a display model. The display model may be created by measuring color and brightness of pixels for various folded configurations, view-points and/or viewing angles.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: August 29, 2023
    Inventors: Yenyu Peng, Yu-Ting Chung
  • Publication number: 20230005402
    Abstract: Foldable displays may have portions folded into a folded configuration. Each folded portion may be observed by a user at a different viewing angle. As such, folding-artifacts may appear in the displayed image as a result of the different viewing angles. For example, a perceptible color difference and/or a perceptible brightness difference may appear between folded portions. Disclosed here are systems and methods to create compensated images that when displayed reduced the folding artifacts. The creation may include sensing a viewing angle for each portion and determining adjustments for pixels in each portion using a display model. The display model may be created by measuring color and brightness of pixels for various folded configurations, view-points and/or viewing angles.
    Type: Application
    Filed: January 24, 2020
    Publication date: January 5, 2023
    Inventors: Yenyu Peng, Yu-Ting Chung
  • Patent number: 11469748
    Abstract: A first current source and a third current source are coupled at a first output node. A second current source and a fourth current source are coupled at a second output node. Control terminals of a first transistor and a second transistor are coupled to the second output node. Control terminals of a third transistor and a fourth transistor are coupled to the first output node. The first transistor and a fifth transistor are coupled in series between a power terminal and the first output node. A sixth transistor and the second transistor are coupled in series between the first output node and a ground terminal. The third transistor and a seventh transistor are coupled in series between the power terminal and the second output node. An eighth transistor and the fourth transistor are coupled in series between the second output node and the ground terminal.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: October 11, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Yu-Ting Chung
  • Publication number: 20220271744
    Abstract: A first current source and a third current source are coupled at a first output node. A second current source and a fourth current source are coupled at a second output node. Control terminals of a first transistor and a second transistor are coupled to the second output node. Control terminals of a third transistor and a fourth transistor are coupled to the first output node. The first transistor and a fifth transistor are coupled in series between a power terminal and the first output node. A sixth transistor and the second transistor are coupled in series between the first output node and a ground terminal. The third transistor and a seventh transistor are coupled in series between the power terminal and the second output node. An eighth transistor and the fourth transistor are coupled in series between the second output node and the ground terminal.
    Type: Application
    Filed: June 15, 2021
    Publication date: August 25, 2022
    Inventor: Yu-Ting CHUNG
  • Patent number: 11050396
    Abstract: An amplifier circuit is provided, which includes an input stage circuit, at least one impedance component and a current supply circuit, where the input stage circuit is coupled between at least one input terminal of the amplifier circuit and at least one output terminal of the amplifier circuit, the impedance component is coupled between a first reference voltage and the output terminal, and the current supply circuit is coupled between a second reference voltage and the output terminal. The input stage circuit is arranged to generate a signal current in response to an input signal on the input terminal, and the current supply circuit is arranged to provide at least one adjustment current. In addition, a common mode voltage level of an output signal on the output terminal is controlled by the adjustment current, to allow the amplifier circuit to perform low voltage operations.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: June 29, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: Yu-Ting Chung, Shawn Min, Yi-Chun Hsieh
  • Publication number: 20200287508
    Abstract: An amplifier circuit is provided, which includes an input stage circuit, at least one impedance component and a current supply circuit, where the input stage circuit is coupled between at least one input terminal of the amplifier circuit and at least one output terminal of the amplifier circuit, the impedance component is coupled between a first reference voltage and the output terminal, and the current supply circuit is coupled between a second reference voltage and the output terminal. The input stage circuit is arranged to generate a signal current in response to an input signal on the input terminal, and the current supply circuit is arranged to provide at least one adjustment current. In addition, a common mode voltage level of an output signal on the output terminal is controlled by the adjustment current, to allow the amplifier circuit to perform low voltage operations.
    Type: Application
    Filed: July 23, 2019
    Publication date: September 10, 2020
    Inventors: Yu-Ting Chung, Shawn Min, Yi-Chun Hsieh