Patents by Inventor Yu-Ting LU

Yu-Ting LU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11950408
    Abstract: A method of manufacturing a semiconductor structure is provided. A conductive layer is formed on a precursor memory structure. A target layer is formed on the conductive layer. A first photoresist with a first opening is formed on the target layer. A spacer is formed on sidewalls of the first opening. A second photoresist with a second opening is formed on the target layer and the spacer. The target layer is patterned by the second photoresist and the spacer to form a first patterned target layer. A third photoresist with a third opening is formed on the first patterned target layer. The first patterned target layer is patterned by the third photoresist to form a second patterned target layer. The conductive layer is patterned by the second patterned target layer to form a patterned conductive layer including a ring structure aligned with a source/drain region.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: April 2, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Hsueh-Han Lu, Yu-Ting Lin
  • Publication number: 20240096781
    Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.
    Type: Application
    Filed: March 20, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Ti Lu, Hao-Yi Tsai, Chia-Hung Liu, Yu-Hsiang Hu, Hsiu-Jen Lin, Tzuan-Horng Liu, Chih-Hao Chang, Bo-Jiun Lin, Shih-Wei Chen, Hung-Chun Cho, Pei-Rong Ni, Hsin-Wei Huang, Zheng-Gang Tsai, Tai-You Liu, Po-Chang Shih, Yu-Ting Huang
  • Patent number: 11923337
    Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: March 5, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching Ho, Bo-Hao Ma, Yu-Ting Xue, Ching-Hung Tseng, Guan-Hua Lu, Hong-Da Chang
  • Publication number: 20240063163
    Abstract: A semiconductor package structure includes a semiconductor device with an active surface, a conductive pillar on the conductive pad, an adhesion strengthening layer, and an encapsulant in contact with the adhesion strengthening layer. The conductive pillar has a side surface and a top surface. The adhesion strengthening layer is conformally disposed on the side surface of the conductive pillar and the active surface of the semiconductor device.
    Type: Application
    Filed: October 31, 2023
    Publication date: February 22, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Pin TSAI, Ming-Chi LIU, Yu-Ting LU, Kai-Chiang HSU, Che-Ting LIU
  • Patent number: 11804461
    Abstract: A semiconductor package structure includes a semiconductor device with an active surface, a conductive pillar on the conductive pad, an adhesion strengthening layer, and an encapsulant in contact with the adhesion strengthening layer. The conductive pillar has a side surface and a top surface. The adhesion strengthening layer is conformally disposed on the side surface of the conductive pillar and the active surface of the semiconductor device.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: October 31, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Ping Tsai, Ming-Chi Liu, Yu-Ting Lu, Kai-Chiang Hsu, Che-Ting Liu
  • Publication number: 20230138460
    Abstract: A method and a system for manufacturing a semiconductor package structure are provided. The method includes: (a) providing a package body including at least one semiconductor device encapsulated in an encapsulant; (b) providing a flattening force to the package body; (c) thinning the package body after (b); (d) attaching a film to the package body; and (e) releasing the flattening force after (d).
    Type: Application
    Filed: December 27, 2022
    Publication date: May 4, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Che-Ting LIU, Jheng-Yu HONG, Yu-Ting LU, Po-Chun LEE, Chih-Hsiang HSU
  • Patent number: 11538787
    Abstract: A method and a system for manufacturing a semiconductor package structure are provided. The method includes: (a) providing a package body including at least one semiconductor device encapsulated in an encapsulant; (b) providing a flattening force to the package body; (c) thinning the package body after (b); (d) attaching a film to the package body; and (e) releasing the flattening force after (d).
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: December 27, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Che-Ting Liu, Jheng-Yu Hong, Yu-Ting Lu, Po-Chun Lee, Chih-Hsiang Hsu
  • Publication number: 20220139872
    Abstract: A method and a system for manufacturing a semiconductor package structure are provided. The method includes: (a) providing a package body including at least one semiconductor device encapsulated in an encapsulant; (b) providing a flattening force to the package body; (c) thinning the package body after (b); (d) attaching a film to the package body; and (e) releasing the flattening force after (d).
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Che-Ting LIU, Jheng-Yu HONG, Yu-Ting LU, Po-Chun LEE, Chih-Hsiang HSU
  • Publication number: 20210407951
    Abstract: A semiconductor package structure includes a semiconductor device with an active surface, a conductive pillar on the conductive pad, an adhesion strengthening layer, and an encapsulant in contact with the adhesion strengthening layer. The conductive pillar has a side surface and a top surface. The adhesion strengthening layer is conformally disposed on the side surface of the conductive pillar and the active surface of the semiconductor device.
    Type: Application
    Filed: September 13, 2021
    Publication date: December 30, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Ping TSAI, Ming-Chi LIU, Yu-Ting LU, Kai-Chiang HSU, Che-Ting LIU
  • Patent number: 11121111
    Abstract: A semiconductor package structure includes a semiconductor device with an active surface, a conductive pillar on the conductive pad, an adhesion strengthening layer, and an encapsulant in contact with the adhesion strengthening layer. The conductive pillar has a side surface and a top surface. The adhesion strengthening layer is conformally disposed on the side surface of the conductive pillar and the active surface of the semiconductor device.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: September 14, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Pin Tsai, Ming-Chi Liu, Yu-Ting Lu, Kai-Chiang Hsu, Che-Ting Liu
  • Patent number: 11088057
    Abstract: A semiconductor package structure includes a wiring structure, a semiconductor module, a protection layer and a plurality of outer conductive vias. The wiring structure includes at least one dielectric layer and at least one redistribution layer. The semiconductor module is electrically connected to the wiring structure. The semiconductor module has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The protection layer covers the lateral surface of the semiconductor module and a surface of the wiring structure. The outer conductive vias surround the lateral surface of the semiconductor module, electrically connect to the wiring structure, and extend through a dielectric layer of the wiring structure and the protection layer.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: August 10, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Pin Tsai, Man-Wen Tseng, Yu-Ting Lu
  • Publication number: 20210074664
    Abstract: A semiconductor package structure includes a semiconductor device with an active surface, a conductive pillar on the conductive pad, an adhesion strengthening layer, and an encapsulant in contact with the adhesion strengthening layer. The conductive pillar has a side surface and a top surface. The adhesion strengthening layer is conformally disposed on the side surface of the conductive pillar and the active surface of the semiconductor device.
    Type: Application
    Filed: September 9, 2019
    Publication date: March 11, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Pin TSAI, Ming-Chi LIU, Yu-Ting LU, Kai-Chiang HSU, Che-Ting LIU
  • Patent number: 10879215
    Abstract: A method for manufacturing a semiconductor device package includes: (1) providing a first encapsulation layer; (2) disposing an adhesive layer on the first encapsulation layer; (3) disposing a first die on the adhesive layer; and (4) forming a second encapsulation layer covering the first die, the adhesive layer, and the first encapsulation layer.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: December 29, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Li-Hao Lyu, Chieh-Ju Tsai, Yu-Kai Lin, Wei-Ming Hsieh, Yu-Pin Tsai, Man-Wen Tseng, Yu-Ting Lu
  • Publication number: 20200357730
    Abstract: A semiconductor package structure includes a wiring structure, a semiconductor module, a protection layer and a plurality of outer conductive vias. The wiring structure includes at least one dielectric layer and at least one redistribution layer. The semiconductor module is electrically connected to the wiring structure. The semiconductor module has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The protection layer covers the lateral surface of the semiconductor module and a surface of the wiring structure. The outer conductive vias surround the lateral surface of the semiconductor module, electrically connect to the wiring structure, and extend through a dielectric layer of the wiring structure and the protection layer.
    Type: Application
    Filed: May 10, 2019
    Publication date: November 12, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Pin TSAI, Man-Wen TSENG, Yu-Ting LU
  • Patent number: 10792767
    Abstract: A laser preheating control method is applied to a laser preheating control device. When a cutter processes a workpiece along a process path, a laser source of the device is provided to output a laser beam to the workpiece for selectively forming a laser spot on the workpiece surface. And according to a movement direction of the cutter, a laser controller of the device is provided to form the laser spot only on a preheating region of the workpiece, where in front of the cutter in the process path, for preheating the workpiece in the preheating region. As a result, the laser spot will not repeatedly heat the workpiece behind the cutter in the process path, and the qualitative change of the workpiece caused by repeating heating is preventable.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: October 6, 2020
    Assignees: Metal Industries Research & Development Centre, Parfaite Tool Co., Ltd.
    Inventors: Yu-Ting Lu, Yu-Fu Lin, Jui-Teng Chen, Wen-Long Chang, Chih-Hung Chou
  • Publication number: 20190206843
    Abstract: A method for manufacturing a semiconductor device package includes: (1) providing a first encapsulation layer; (2) disposing an adhesive layer on the first encapsulation layer; (3) disposing a first die on the adhesive layer; and (4) forming a second encapsulation layer covering the first die, the adhesive layer, and the first encapsulation layer.
    Type: Application
    Filed: March 8, 2019
    Publication date: July 4, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Li-Hao LYU, Chieh-Ju TSAI, Yu-Kai LIN, Wei-Ming HSIEH, Yu-Pin TSAI, Man-Wen TSENG, Yu-Ting LU
  • Publication number: 20190143457
    Abstract: A laser preheating control method is applied to a laser preheating control device. When a cutter processes a workpiece along a process path, a laser source of the device is provided to output a laser beam to the workpiece for selectively forming a laser spot on the workpiece surface. And according to a movement direction of the cutter, a laser controller of the device is provided to form the laser spot only on a preheating region of the workpiece, where in front of the cutter in the process path, for preheating the workpiece in the preheating region. As a result, the laser spot will not repeatedly heat the workpiece behind the cutter in the process path, and the qualitative change of the workpiece caused by repeating heating is preventable.
    Type: Application
    Filed: December 26, 2017
    Publication date: May 16, 2019
    Inventors: Yu-Ting Lu, Yu-Fu Lin, Jui-Teng Chen, Wen-Long Chang, Chih-Hung Chou
  • Patent number: 10269771
    Abstract: A semiconductor device package comprises an adhesive layer, a die on the adhesive layer, a first encapsulation layer encapsulating the die and the adhesive layer, and a second encapsulation layer adjacent to the first encapsulation layer and the adhesive layer. The second encapsulation layer has a first surface and a second surface different from the first surface. A contact angle of the first surface of the second encapsulation layer is different from a contact angle of the second surface of the second encapsulation layer.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: April 23, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Li-Hao Lyu, Chieh-Ju Tsai, Yu-Kai Lin, Wei-Ming Hsieh, Yu-Pin Tsai, Man-Wen Tseng, Yu-Ting Lu
  • Publication number: 20180178322
    Abstract: A laser process device includes a processing machinery for processing a workpiece, a laser source for emitting a laser beam to the workpiece and a modulating lens group. The modulating lens group can selectively modulate the laser beam for laser processing the workpiece respectively, like pre-heating, forming process or post treatment, so the modulating lens group can improve process efficiency of the processing machinery.
    Type: Application
    Filed: December 28, 2016
    Publication date: June 28, 2018
    Inventors: Yu-Ting Lu, Chao-Yung Yeh, Chiu-Feng Lin, Ying-Cheng Lu
  • Publication number: 20180061727
    Abstract: A semiconductor device package comprises an adhesive layer, a die on the adhesive layer, a first encapsulation layer encapsulating the die and the adhesive layer, and a second encapsulation layer adjacent to the first encapsulation layer and the adhesive layer. The second encapsulation layer has a first surface and a second surface different from the first surface. A contact angle of the first surface of the second encapsulation layer is different from a contact angle of the second surface of the second encapsulation layer.
    Type: Application
    Filed: August 11, 2017
    Publication date: March 1, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Li-Hao LYU, Chieh-Ju TSAI, Yu-Kai LIN, Wei-Ming HSIEH, Yu-Pin TSAI, Man-Wen TSENG, Yu-Ting LU