Patents by Inventor Yu Ting Tsai
Yu Ting Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145571Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.Type: ApplicationFiled: January 5, 2023Publication date: May 2, 2024Inventors: Po-Ting Lin, Yu-Ming Hsiang, Wei-Chih Wen, Yin-Hao Wu, Wu-Wei Tsai, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
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Publication number: 20240145561Abstract: A semiconductor may include an active region, an epitaxial source/drain formed in and extending above the active region, and a first dielectric layer formed over a portion of the active region. The semiconductor may include a first metal gate and a second metal gate formed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer and the second metal gate, and a titanium layer, without an intervening fluorine residual layer, formed on the metal gate and the epitaxial source/drain. The semiconductor may include a first metal layer formed on top of the titanium on the first metal gate, a second metal layer formed on top of the titanium layer on the epitaxial source/drain, and a third dielectric layer formed on the second dielectric layer. The semiconductor may include first and second vias formed in the third dielectric layer.Type: ApplicationFiled: January 10, 2024Publication date: May 2, 2024Inventors: Yu-Ting TSAI, Chung-Liang CHENG, Hong-Ming LO, Chun-Chih LIN, Chyi-Tsong NI
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Publication number: 20240147711Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Inventors: PERNG-FEI YUH, YIH WANG, MENG-SHENG CHANG, JUI-CHE TSAI, KU-FENG LIN, YU-WEI LIN, KEH-JENG CHANG, CHANSYUN DAVID YANG, SHAO-TING WU, SHAO-YU CHOU, PHILEX MING-YAN FAN, YOSHITAKA YAMAUCHI, TZU-HSIEN YANG
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Patent number: 11950424Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first gate electrode disposed on the substrate and located in a first region of the semiconductor device. The semiconductor device also includes a first sidewall structure covering the first gate electrode. The semiconductor device further includes a protective layer disposed between the first gate electrode and the first sidewall structure. In addition, the semiconductor device includes a second gate electrode disposed on the substrate and located in a second region of the semiconductor device. The semiconductor device also includes a second sidewall structure covering a lateral surface of the second gate electrode.Type: GrantFiled: June 7, 2021Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Ting Tsai, Ching-Tzer Weng, Tsung-Hua Yang, Kao-Chao Lin, Chi-Wei Ho, Chia-Ta Hsieh
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Publication number: 20240101847Abstract: A quantum dot oil-based ink is provided. The quantum dot oil-based ink includes a quantum dot material, a dispersing solvent, a viscosity modifier, and a surface tension modifying solution. The dispersing solvent includes a linear alkane having 6 to 14 carbon atoms. The viscosity modifier includes an aromatic hydrocarbon having 10 to 18 carbon atoms or a linear olefin having 16 to 20 carbon atoms. The surface tension modifying solution includes a hydrophobic polymer material and a nonpolar solvent.Type: ApplicationFiled: November 29, 2022Publication date: March 28, 2024Inventors: Chun Che LIN, Chong-Ci HU, Yi-Ting TSAI, Ching-Yi CHEN, Yu-Chun LEE
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Publication number: 20240096781Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.Type: ApplicationFiled: March 20, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Ti Lu, Hao-Yi Tsai, Chia-Hung Liu, Yu-Hsiang Hu, Hsiu-Jen Lin, Tzuan-Horng Liu, Chih-Hao Chang, Bo-Jiun Lin, Shih-Wei Chen, Hung-Chun Cho, Pei-Rong Ni, Hsin-Wei Huang, Zheng-Gang Tsai, Tai-You Liu, Po-Chang Shih, Yu-Ting Huang
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Patent number: 11908909Abstract: A semiconductor may include an active region, an epitaxial source/drain formed in and extending above the active region, and a first dielectric layer formed over a portion of the active region. The semiconductor may include a first metal gate and a second metal gate formed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer and the second metal gate, and a titanium layer, without an intervening fluorine residual layer, formed on the metal gate and the epitaxial source/drain. The semiconductor may include a first metal layer formed on top of the titanium on the first metal gate, a second metal layer formed on top of the titanium layer on the epitaxial source/drain, and a third dielectric layer formed on the second dielectric layer. The semiconductor may include first and second vias formed in the third dielectric layer.Type: GrantFiled: July 29, 2022Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Ting Tsai, Chung-Liang Cheng, Hong-Ming Lo, Chun-Chih Lin, Chyi-Tsong Ni
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Publication number: 20230268227Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a dielectric layer defining an opening, an adhesion layer in the opening, and a conductive layer in the opening over the adhesion layer. A material of the conductive layer is a same material as an adhesion material of the adhesion layer.Type: ApplicationFiled: April 27, 2023Publication date: August 24, 2023Inventors: Yu-Ting TSAI, Chung-Liang Cheng, Ching-Jing Wu, Chyi-Tsong Ni
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Patent number: 11670547Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a dielectric layer defining an opening, an adhesion layer in the opening, and a conductive layer in the opening over the adhesion layer. A material of the conductive layer is a same material as an adhesion material of the adhesion layer.Type: GrantFiled: January 15, 2021Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Ting Tsai, Chung-Liang Cheng, Ching-Jing Wu, Chyi-Tsong Ni
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Publication number: 20230017955Abstract: A system and method for cleaning a preclean process chamber in between wafer processing. The internal pressure of the preclean process chamber is reduced to a first pressure and a first gas that consists of oxygen and an inert or noble gas, is introduced into the chamber. Plasma is generated within the preclean process chamber using the first gas at the first pressure. Internal pressure is then reduced to a second pressure, less than the first, and the first gas is continued into the chamber. Plasma is then generated using the first gas at the second pressure. Thereafter, a second gas, consisting of an oxygen-free inert or noble gas, is introduced into the chamber at the second pressure, following which plasma is generated within the chamber using only the second gas.Type: ApplicationFiled: February 24, 2022Publication date: January 19, 2023Inventors: Yu-Ting Tsai, Hung-Chih Wang, Hong-Ming Lo, Shao-Shuo Wu, Su-Yu Yeh
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Publication number: 20220392912Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first gate electrode disposed on the substrate and located in a first region of the semiconductor device. The semiconductor device also includes a first sidewall structure covering the first gate electrode. The semiconductor device further includes a protective layer disposed between the first gate electrode and the first sidewall structure. In addition, the semiconductor device includes a second gate electrode disposed on the substrate and located in a second region of the semiconductor device. The semiconductor device also includes a second sidewall structure covering a lateral surface of the second gate electrode.Type: ApplicationFiled: June 7, 2021Publication date: December 8, 2022Inventors: Yu-Ting Tsai, Ching-Tzer Weng, Tsung-Hua Yang, Kao-Chao Lin, Chi-Wei Ho, Chia-Ta Hsieh
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Publication number: 20220384592Abstract: A semiconductor may include an active region, an epitaxial source/drain formed in and extending above the active region, and a first dielectric layer formed over a portion of the active region. The semiconductor may include a first metal gate and a second metal gate formed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer and the second metal gate, and a titanium layer, without an intervening fluorine residual layer, formed on the metal gate and the epitaxial source/drain. The semiconductor may include a first metal layer formed on top of the titanium on the first metal gate, a second metal layer formed on top of the titanium layer on the epitaxial source/drain, and a third dielectric layer formed on the second dielectric layer. The semiconductor may include first and second vias formed in the third dielectric layer.Type: ApplicationFiled: July 29, 2022Publication date: December 1, 2022Inventors: Yu-Ting TSAI, Chung-Liang CHENG, Hong-Ming LO, Chun-Chih LIN, Chyi-Tsong NI
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Publication number: 20220298634Abstract: An apparatus for manufacturing a semiconductor device may include a chamber, a chuck provided in the chamber, and a biased power supply physically connected with the chuck. The apparatus may include a target component provided over the chuck and the biased power supply, and a magnetron assembly provided over the target component. The magnetron assembly may include a plurality of outer magnetrons and a plurality of inner magnetrons, and a spacing between each adjacent magnetrons of the plurality of outer magnetrons may be different from a spacing between each adjacent magnetrons of the plurality of inner magnetrons.Type: ApplicationFiled: March 18, 2021Publication date: September 22, 2022Inventors: Yu-Ting TSAI, Chung-Liang CHENG, Wen-Cheng CHENG, Che-Hung LIU, Yu-Cheng SHEN, Chyi-Tsong NI
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Patent number: 11437477Abstract: A semiconductor may include an active region, an epitaxial source/drain formed in and extending above the active region, and a first dielectric layer formed over a portion of the active region. The semiconductor may include a first metal gate and a second metal gate formed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer and the second metal gate, and a titanium layer, without an intervening fluorine residual layer, formed on the metal gate and the epitaxial source/drain. The semiconductor may include a first metal layer formed on top of the titanium layer on the first metal gate, a second metal layer formed on top of the titanium layer on the epitaxial source/drain, and a third dielectric layer formed on the second dielectric layer. The semiconductor may include first and second vias formed in the third dielectric layer.Type: GrantFiled: April 8, 2021Date of Patent: September 6, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Ting Tsai, Chung-Liang Cheng, Hong-Ming Lo, Chun-Chih Lin, Chyi-Tsong Ni
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Publication number: 20220230914Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a dielectric layer defining an opening, an adhesion layer in the opening, and a conductive layer in the opening over the adhesion layer. A material of the conductive layer is a same material as an adhesion material of the adhesion layer.Type: ApplicationFiled: January 15, 2021Publication date: July 21, 2022Inventors: Yu-Ting Tsai, Chung-Liang Cheng, Allen Wu, Chyi-Tsong Ni
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Patent number: 11336215Abstract: A display including a supporting stand and a display panel is provided. The supporting stand has a rotating assembly, a drive motor, and a microcontroller. The display panel has a computing device. The drive motor is connected to the rotating assembly for driving the rotating assembly to rotate. The microcontroller is coupled to the drive motor for controlling the drive motor. The display panel is disposed on the rotating assembly. The computing device is coupled to the microcontroller. The computing device is configured to read an image. The computing device transmits a signal to the microcontroller based on an orientation of the image being portrait or landscape so that the microcontroller switches on the drive motor and the rotating assembly drives the display panel to rotate relative to the supporting stand for switching a rotating position of the display panel to a portrait mode or a landscape mode.Type: GrantFiled: October 26, 2020Date of Patent: May 17, 2022Assignee: PEGATRON CORPORATIONInventors: Tai-Jung Huang, Pei-Chin Wang, Chien-Sheng Lo, Yu-Lin Fang, Yu-Ting Tsai
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Publication number: 20210152114Abstract: A display including a supporting stand and a display panel is provided. The supporting stand has a rotating assembly, a drive motor, and a microcontroller. The display panel has a computing device. The drive motor is connected to the rotating assembly for driving the rotating assembly to rotate. The microcontroller is coupled to the drive motor for controlling the drive motor. The display panel is disposed on the rotating assembly. The computing device is coupled to the microcontroller. The computing device is configured to read an image. The computing device transmits a signal to the microcontroller based on an orientation of the image being portrait or landscape so that the microcontroller switches on the drive motor and the rotating assembly drives the display panel to rotate relative to the supporting stand for switching a rotating position of the display panel to a portrait mode or a landscape mode.Type: ApplicationFiled: October 26, 2020Publication date: May 20, 2021Applicant: PEGATRON CORPORATIONInventors: Tai-Jung Huang, Pei-Chin Wang, Chien-Sheng Lo, Yu-Lin Fang, Yu-Ting Tsai
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Publication number: 20140098965Abstract: A method discloses measuring electroacoustic parameters of transducer. With known voice-coil displacement, voice-coil current, transducer impedance and its stimulus signal as inputs, the five calculation procedures of direct problem, adjoint problem, sensitivity problem, conjugate gradient method, and constraint equations are involved in inversely solving electroacoustic parameters. The presented method has the characteristics of high efficiently, low iterations for computational algorithm, and high accuracy for electroacoustic parameters estimation. Through the numerical result and discussion, the relative errors between estimated and accurate electroacoustic parameters are sufficiently small even with the inclusion of the inevitable measurement errors. These results indicate that the presented method has high feasibility for estimating electroacoustic parameters of a transducer.Type: ApplicationFiled: December 27, 2012Publication date: April 10, 2014Applicant: FENG CHIA UNIVERSITYInventors: Chi-Chang WANG, Jin-Huang HUANG, Yu-Ting TSAI
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Patent number: D813295Type: GrantFiled: October 19, 2016Date of Patent: March 20, 2018Assignee: TEAM INTERNATIONAL MUSIC CO., LTD.Inventor: Yu-Ting Tsai
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Patent number: D818523Type: GrantFiled: June 16, 2016Date of Patent: May 22, 2018Assignee: TEAM INTERNATIONAL MUSIC CO., LTD.Inventor: Yu-Ting Tsai