Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack comprising a plurality of dielectric layer pairs disposed over a substrate; forming a first mask stack over the alternating layer stack; patterning the first mask stack to define a staircase region comprising a number of N sub-staircase regions over the alternating layer stack using a lithography process and N is greater than 1; forming a first staircase structure over the staircase region, the first staircase structure has a number of M steps at each of the staircase regions and M is greater than 1; and forming a second staircase structure on the first staircase structure, the second staircase structure has a number of 2*N*M steps at the staircase region.

Abstract: Embodiments of three-dimensional (3D) memory devices having a memory layer that confines electron transportation and methods for forming the same are disclosed. A method for forming a 3D memory device includes the following operations. First, an initial channel hole can be formed in a structure. The structure can include a staircase structure. The structure can include a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset can be formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel can then be formed based on the channel hole. Further, a plurality of gate electrodes can be formed based on the plurality of second layers.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate and a multiple-stack staircase structure. The multiple-stack staircase structure can include a plurality of staircase structures stacked over the substrate. Each one of the plurality of staircase structures can include a plurality of conductor layers each between two insulating layers. The memory device can also include a filling structure over the multiple-stack staircase structure, a semiconductor channel extending through the multiple-stack staircase structure, and a supporting pillar extending through the multiple-stack staircase structure and the filling structure. The semiconductor channel can include unaligned sidewall surfaces, and the supporting pillar can include aligned sidewall surfaces.

Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack.

Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack comprising a plurality of dielectric layer pairs disposed over a substrate; forming a first mask stack over the alternating layer stack; patterning the first mask stack to define a staircase region comprising a number of N sub-staircase regions over the alternating layer stack using a lithography process and N is greater than 1; forming a first staircase structure over the staircase region, the first staircase structure has a number of M steps at each of the staircase regions and M is greater than 1; and forming a second staircase structure on the first staircase structure, the second staircase structure has a number of 2 * N * M steps at the staircase region.

Abstract: Disclosed is a method for forming a staircase structure of 3D memory devices, comprising (i) forming a stack of layers on a substrate; (ii) removing a portion of the stack to form a lower region and a upper region; (iii) forming a mask to cover the lower region and the upper region of the stack; (iv) forming a first opening in the mask to expose a first portion of the stack in the lower region and a second opening in the mask to expose a second portion of the stack in the upper region; (v) forming a photoresist layer to cover the stack and the mask; (vi) using a same set of trim-etch processes to pattern the photoresist layer to form a set of staircases in the first opening and the second opening; (vii) removing the photoresist layer and the mask; and repeating (iii), (iv), (v), (vi) and (vii) sequentially.

Abstract: Embodiments of three-dimensional (3D) memory devices having a memory layer that confines electron transportation and methods for forming the same are disclosed. A method for forming a 3D memory device includes the following operations. First, an initial channel hole can be formed in a structure. The structure can include a staircase structure. The structure can include a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset can be formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel can then be formed based on the channel hole. Further, a plurality of gate electrodes can be formed based on the plurality of second layers.

Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a first alternating conductor/dielectric stack disposed on the substrate and a layer of silicon carbide disposed over the first alternating conductor/dielectric stack. A second alternating conductor/dielectric stack is disposed on the silicon carbide layer. The memory device includes one or more first structures extending orthogonally with respect to the surface of the substrate through the first alternating conductor/dielectric stack and over the epitaxially-grown material disposed in the plurality of recesses, and one or more second structures extending orthogonally with respect to the surface of the substrate through the second alternating conductor/dielectric stack. The one or more second structures are substantially aligned over corresponding ones of the one or more first structures.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate and a multiple-stack staircase structure. The multiple-stack staircase structure can include a plurality of staircase structures stacked over the substrate. Each one of the plurality of staircase structures can include a plurality of conductor layers each between two insulating layers. The memory device can also include a filling structure over the multiple-stack staircase structure, a semiconductor channel extending through the multiple-stack staircase structure, and a supporting pillar extending through the multiple-stack staircase structure and the filling structure. The semiconductor channel can include unaligned sidewall surfaces, and the supporting pillar can include aligned sidewall surfaces.

Abstract: Embodiments of a method for forming a staircase structure of 3D memory devices are disclosed. The method comprises (i) forming an alternating layer stack including multiple layers disposed on a substrate in a vertical direction; (ii) removing a portion of the alternating layer stack to form multiple step-platforms in a staircase region of the alternating layer stack; (iii) forming a hard mask layer to cover top surfaces of the step-platforms; (iv) forming multiple openings in the hard mask layer to expose a portion of each of the step-platforms; (v) forming a photoresist layer to cover the top surfaces of the step-platforms and the hard mask layer; (vi) using a same set of trim-etch processes to pattern the photoresist layer to form a set of staircases on each of the step-platforms; (vii) removing the photoresist layer and the hard mask layer; and repeating (iii), (iv), (v), (vi) and (vii) sequentially.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a first alternating conductor/dielectric stack disposed on the substrate and a layer of silicon carbide disposed over the first alternating conductor/dielectric stack. A second alternating conductor/dielectric stack is disposed on the silicon carbide layer. The memory device includes one or more first structures extending orthogonally with respect to the surface of the substrate through the first alternating conductor/dielectric stack and over the epitaxially-grown material disposed in the plurality of recesses, and one or more second structures extending orthogonally with respect to the surface of the substrate through the second alternating conductor/dielectric stack. The one or more second structures are substantially aligned over corresponding ones of the one or more first structures.

Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack.

Abstract: Embodiments of a method for forming a staircase structure of 3D memory devices are disclosed. The method comprises (i) forming an alternating layer stack including multiple layers disposed on a substrate in a vertical direction; (ii) removing a portion of the alternating layer stack to form multiple step-platforms in a staircase region of the alternating layer stack; (iii) forming a hard mask layer to cover top surfaces of the step-platforms; (iv) forming multiple openings in the hard mask layer to expose a portion of each of the step-platforms; (v) forming a photoresist layer to cover the top surfaces of the step-platforms and the hard mask layer; (vi) using a same set of trim-etch processes to pattern the photoresist layer to form a set of staircases on each of the step-platforms; (vii) removing the photoresist layer and the hard mask layer; and repeating (iii), (iv), (v), (vi) and (vii) sequentially.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.