Abstract: A flash memory storage apparatus is provided. The flash memory storage apparatus includes a substrate, a control and storage circuit unit, a ground lead, at least a signal lead, and a power lead. The control and storage circuit unit, the power lead, the signal lead, and the ground lead are disposed on the substrate, in which the power lead, the signal lead, and the ground lead respectively electrically connect to the control and storage circuit unit. Moreover, the flash memory storage apparatus further includes an extra ground lead electrically connected to the ground lead or a protrusion on the substrate, such that the ground lead first electrically connects to a host when the flash memory storage apparatus is plugged into the host.

Abstract: A flash memory storage apparatus is provided. The flash memory storage apparatus includes a substrate, a control and storage circuit unit, a ground lead, at least a signal lead, and a power lead. The control and storage circuit unit, the power lead, the signal lead, and the ground lead are disposed on the substrate, in which the power lead, the signal lead, and the ground lead respectively electrically connect to the control and storage circuit unit. Moreover, the flash memory storage apparatus further includes an extra ground lead electrically connected to the ground lead or a protrusion on the substrate, such that the ground lead first electrically connects to a host when the flash memory storage apparatus is plugged into the host.

Abstract: A flash memory storage apparatus is provided. The flash memory storage apparatus includes a substrate, a control and storage circuit unit, a ground lead, at least a signal lead, and a power lead. The control and storage circuit unit, the power lead, the signal lead, and the ground lead are disposed on the substrate, in which the power lead, the signal lead, and the ground lead respectively electrically connect to the control and storage circuit unit. Moreover, the flash memory storage apparatus further includes an extra ground lead electrically connected to the ground lead or a protrusion on the substrate, such that the ground lead first electrically connects to a host when the flash memory storage apparatus is plugged into the host.

Abstract: A driving circuit of an input/output (I/O) interface is provided. The driving circuit includes a main output stage and an enhancing unit. The main output stage receives at least one driving signal and outputs an output signal corresponding to an input signal accordingly. The enhancing unit is coupled to the main output stage. The enhancing unit receives and detects the level of the output signal so as to drive the output force of the main output stage in a first output level or a second output level, wherein the first output level is higher than the second output level.

Abstract: An oscillation circuit, a driving circuit thereof, and a driving method thereof are provided. The driving circuit generates a second enable signal according to an output signal of an oscillator and a first enable signal. The second enable signal is transmitted to the oscillator. When a number of waves of the output signal within a predetermined period is smaller than a predetermined value, the driving circuit adjusts a voltage level of the second enable signal. A voltage level of the first enable signal is equal to an enable voltage level. Through variations in voltage levels of the second enable signal, the oscillator is triggered to oscillate.

Abstract: A random number generator and a random number generating method thereof are provided. The random number generator includes a signal generating unit and a sampling unit. The signal generating unit is adapted for memorizing a status of a noise generated during a transient of an output signal of an output buffer, and accordingly generating a frequency conversion signal which changes according to time and ambient factors. The sampling unit is coupled to the signal generating unit for receiving the frequency conversion signal, and sampling the frequency conversion signal according to a sampling clock pulse, so as to obtain a plurality of sets of unpredictable random number codes.

Abstract: A driving circuit of an input/output (I/O) interface is provided. The driving circuit includes a main output stage and an enhancing unit. The main output stage receives at least one driving signal and outputs an output signal corresponding to an input signal accordingly. The enhancing unit is coupled to the main output stage. The enhancing unit receives and detects the level of the output signal so as to drive the output force of the main output stage in a first output level or a second output level, wherein the first output level is higher than the second output level.

Abstract: A hot plug electronic device with high using safety is provided. The hot plug electronic device includes an operation circuit, a voltage regulator and an over-thermal protection device. The operation circuit is used for communicating with an external host. The voltage regulator is coupled to the operation circuit for supplying power to the operation circuit. The over-thermal protection device is coupled to the voltage regulator for sensing the present temperature of the hot plug electronic device, and accordingly controlling the voltage regulator to normally supply/stop supplying the power to the operation circuit.

Abstract: An oscillator, a driving circuit and an oscillation method are provided. The driving circuit and a crystal are coupled in parallel to generate a clock signal. The driving circuit includes a buffer unit and a control unit. The buffer unit is coupled in parallel to the crystal, and used to amplify an oscillation signal outputted from the crystal to generate the clock signal. The control unit is coupled to the buffer unit, and used to generate a control signal to the buffer unit. The control unit determines a voltage level of the control signal by detecting whether the clock signal or the oscillation signal satisfies an oscillation condition of the crystal, so as to control a gain value of the buffer unit. Therefore, noise of different frequency bands loaded into the clock signal can be avoided.

Abstract: An oscillation circuit, a driving circuit thereof, and a driving method thereof are provided. The driving circuit generates a second enable signal according to an output signal of an oscillator and a first enable signal. The second enable signal is transmitted to the oscillator. When a wave number of the output signal is smaller than a predetermined value during a predetermined period, the driving circuit adjusts a voltage level of the second enable signal. A voltage level of the first enable signal is equal to an enable voltage level. Through variations in voltage levels of the second enable signal, the oscillator is triggered to oscillate.

Abstract: A flash memory storage apparatus is provided. The flash memory storage apparatus includes a substrate, a control and storage circuit unit, a ground lead, at least a signal lead, and a power lead. The control and storage circuit unit, the power lead, the signal lead, and the ground lead are disposed on the substrate, in which the power lead, the signal lead, and the ground lead respectively electrically connect to the control and storage circuit unit. Moreover, the flash memory storage apparatus further includes an extra ground lead electrically connected to the ground lead or a protrusion on the substrate, such that the ground lead first electrically connects to a host when the flash memory storage apparatus is plugged into the host.

Abstract: An oscillator, a driving circuit and an oscillation method are provided. The driving circuit and a crystal are coupled in parallel to generate a clock signal. The driving circuit includes a buffer unit and a control unit. The buffer unit is coupled in parallel to the crystal, and used to amplify an oscillation signal outputted from the crystal to generate the clock signal. The control unit is coupled to the buffer unit, and used to generate a control signal to the buffer unit. The control unit determines a voltage level of the control signal by detecting whether the clock signal or the oscillation signal satisfies an oscillation condition of the crystal, so as to control a gain value of the buffer unit. Therefore, noise of different frequency bands loaded into the clock signal can be avoided.

Abstract: A hot plug electronic device with high using safety is provided. The hot plug electronic device includes an operation circuit, a voltage regulator and an over-thermal protection device. The operation circuit is used for communicating with an external host. The voltage regulator is coupled to the operation circuit for supplying power to the operation circuit. The over-thermal protection device is coupled to the voltage regulator for sensing the present temperature of the hot plug electronic device, and accordingly controlling the voltage regulator to normally supply/stop supplying the power to the operation circuit.

Abstract: A random number generator and a random number generating method thereof are provided. The random number generator includes a signal generating unit and a sampling unit. The signal generating unit is adapted for memorizing a status of a noise generated during a transient of an output signal of an output buffer, and accordingly generating a frequency conversion signal which changes according to time and ambient factors. The sampling unit is coupled to the signal generating unit for receiving the frequency conversion signal, and sampling the frequency conversion signal according to a sampling clock pulse, so as to obtain a plurality of sets of unpredictable random number codes.

Abstract: A converter circuit is provided herein. In the converter, a voltage converting unit receives an input voltage and outputs an output voltage according to the magnitude of the input voltage by switching operation based on a control clock signal. A comparing circuit generates a power good pulse signal by comparing the output voltage with a reference voltage. A pulse width frequency modulation circuit receives the power good pulse signal and a source clock signal to provide the control clock signal. The pulse width of the source clock signal is varied gradually and the frequency of the source clock signal is also changed during a period that the power good pulse signal remains in the first logic state, and the pulse width frequency modulated source clock signal is output as the control clock signal.

Abstract: A programmable detection adjuster is disclosed. The programmable detection adjuster comprises a bandgap and an adjusting circuit. The bandgap comprises a power input terminal, a voltage output terminal, a main resistance and a plurality of resistors. The adjusting circuit comprises a plurality of adjusting resistors, a plurality of transistor switches, a logic controller and detection circuits; said adjusting resistors connected to the main resistance of the bandgap in series. The adjusting resistors are respectively connected to the transistor switch in parallel. The transistor switches are connected to the logic controller. The logic controller is respectively connected to the detection circuits. The detection circuit detects the corresponding resistances in the detection circuit and outputs a voltage level to the logic controller to enable the logic controller to control a conduction of the transistor switches according to a logic conversion table.

Abstract: A programmable detection adjuster is disclosed. The programmable detection adjuster comprises a bandgap and an adjusting circuit. The bandgap comprises a power input terminal, a voltage output terminal, a main resistance and a plurality of resistors. The adjusting circuit comprises a plurality of adjusting resistors, a plurality of transistor switches, a logic controller and detection circuits; said adjusting resistors connected to the main resistance of the bandgap in series. The adjusting resistors are respectively connected to the transistor switch in parallel. The transistor switches are connected to the logic controller. The logic controller is respectively connected to the detection circuits. The detection circuit detects the corresponding resistances in the detection circuit and outputs a voltage level to the logic controller to enable the logic controller to control a conduction of the transistor switches according to a logic conversion table.

Abstract: A voltage detection circuit for detecting the voltage level of a first power source. A first transistor includes a first gate, a first source, and a first drain coupled to the first gate. A second transistor includes a second gate, a second source, and a second drain coupled to the second gate. A comparator includes a first input terminal, a second input terminal coupled to the second drain, and an output terminal. A first resistor is coupled between the first input terminal and the first drain. A second resistor is coupled to the first power source. A third resistor is coupled between the second resistor and the first input terminal. A fourth resistor is coupled between the second resistor and input terminal. A fifth resistor is coupled between the first source, and a second power source. A resistive device is coupled between the first source, and the first power source.

Abstract: A voltage detection circuit for detecting the voltage level of a first power source. A first transistor includes a first gate, a first source, and a first drain coupled to the first gate. A second transistor includes a second gate, a second source, and a second drain coupled to the second gate. A comparator includes a first input terminal, a second input terminal coupled to the second drain, and an output terminal. A first resistor is coupled between the first input terminal and the first drain. A second resistor is coupled to the first power source. A third resistor is coupled between the second resistor and the first input terminal. A fourth resistor is coupled between the second resistor and input terminal. A fifth resistor is coupled between the first source, and a second power source. A resistive device is coupled between the first source, and the first power source.

Abstract: A voltage detection circuit for detecting the voltage level of a first power source. A first transistor includes a first gate, a first source, and a first drain coupled to the first gate. A second transistor includes a second gate, a second source, and a second drain coupled to the second gate. A comparator includes a first input terminal, a second input terminal coupled to the second drain, and an output terminal. A first resistor is coupled between the first input terminal and the first drain. A second resistor is coupled to the first power source. A third resistor is coupled between the second resistor and the first input terminal. A fourth resistor is coupled between the second resistor and input terminal. A fifth resistor is coupled between the first source, and a second power source. A resistive device is coupled between the first source, and the first power source.