Patents by Inventor Yu Tsao
Yu Tsao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240153842Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.Type: ApplicationFiled: January 4, 2024Publication date: May 9, 2024Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu
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Patent number: 11956151Abstract: A transmission control protocol (TCP) flow control method is provided, which comprises: sending a data packet from a packet processor to a receiver and storing a copy of the data packet; receiving a current ACK packet with a current packet number; determining whether the current packet number is identical to a last packet number and whether a last substitute ACK packet generated by the input ACK filter exists; and performing steps respectively corresponding to different results of this determination to avoid TCP congestion control timely. A TCP flow control device performing the method is also disclosed.Type: GrantFiled: December 22, 2021Date of Patent: April 9, 2024Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Po-Jui Tsao, Chuan-Yu Cho, Chun-Chieh Huang
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Publication number: 20240113345Abstract: A battery module and a short protection method thereof are provided. The battery module has a battery cell pack and a control circuit. The method includes: detecting a temperature of the battery cell pack as a battery cell temperature through the control circuit; determining whether the battery cell temperature shows a downward trend when the battery cell temperature is higher than a first predetermined temperature value; and deactivating the battery module when the battery cell temperature does not show the downward trend.Type: ApplicationFiled: May 23, 2023Publication date: April 4, 2024Applicant: ASUSTeK COMPUTER INC.Inventors: Chunyen Lai, Yu-Cheng Shen, Chun Tsao, Chaochan Tan, Huichuan Lo, Wen-Che Chung, Ming Hung Yao
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Patent number: 11948800Abstract: A device includes a pair of gate spacers on a substrate, and a gate structure on the substrate and between the gate spacers. The gate structure includes an interfacial layer, a metal oxide layer, a nitride-containing layer, a tungsten-containing layer, and a metal compound layer. The interfacial layer is over the substrate. The metal oxide layer is over the interfacial layer. The nitride-containing layer is over the metal oxide layer. The tungsten-containing layer is over the nitride-containing layer. The metal compound layer is over the tungsten-containing layer. The metal compound layer has a different material than a material of the tungsten-containing layer.Type: GrantFiled: December 14, 2022Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Yu Chen, Yu-Chi Lu, Chih-Pin Tsao, Shih-Hsun Chang
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Publication number: 20240105642Abstract: A method of manufacturing a package structure at least includes the following steps. An encapsulant laterally is formed to encapsulate the die and the plurality of through vias. A plurality of first connectors are formed to electrically connect to first surfaces of the plurality of through vias. A warpage control material is formed over the die, wherein the warpage control material is disposed to cover an entire surface of the die. A protection material is formed over the encapsulant and around the plurality of first connectors and the warpage control material. A coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.Type: ApplicationFiled: November 29, 2023Publication date: March 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Jan Pei, Ching-Hua Hsieh, Hsiu-Jen Lin, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Jen-Jui Yu, Cheng-Shiuan Wong
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Publication number: 20240085934Abstract: In some embodiments, an integrated circuit device includes multiple rows of functional cells, with each row having a cell height. At least one of rows of functional cells includes at least one digital low-dropout voltage regulator (DLVR) cell with the cell height for the row. The DLVR cell includes: an input terminal, an output terminal, a voltage supply terminal, a reference voltage terminal, and one or more pairs of transistors. Each pair of transistors are arranged in cascode configuration connected between the voltage supply terminal and output terminal. The gate of one of the transistors the cascode configuration is connected to the input terminal, and the gate of the other transistor in the cascode configuration is connected to the reference voltage terminal. The four terminals each comprises a metal track in the bottom metal layer and disposed within the cell height.Type: ApplicationFiled: August 18, 2023Publication date: March 14, 2024Inventors: Po-Yu LAI, Szu-Chun TSAO, Jaw-Juinn HORNG
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Publication number: 20240088062Abstract: A package structure includes a die, an encapsulant laterally encapsulating the die, a warpage control material disposed over the die, and a protection material disposed over the encapsulant and around the warpage control material. A coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.Type: ApplicationFiled: November 23, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Jan Pei, Ching-Hua Hsieh, Hsiu-Jen Lin, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Jen-Jui Yu, Cheng-Shiuan Wong
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Publication number: 20230332087Abstract: Examples of the present disclosure generally relate to systems, methods, and devices for performing electrochemical control and monitoring of bacterial gene expression to a precisely assigned level, and may be used, for example, for controlling the production of a protein of interest.Type: ApplicationFiled: April 14, 2023Publication date: October 19, 2023Applicant: University of Maryland, College ParkInventors: John Robertson Rzasa, Sally Wang, Chen-Yu Chen, Chen-Yu Tsao, William E. Bentley
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Publication number: 20230245860Abstract: A diffusing plate includes a plate body including a rectangular hole-configuring region, a plurality of holes arranged in the rectangular hole-configuring region and arranged concentrically to form a first to an N-th rectangular patterns from an inside to an outside sequentially. Scales of the first to the N-th rectangular patterns are incrementally increased, and N is a positive integer. One portion of the holes are located in an area near a center of the rectangular hole-configuring region, another portion of the holes are located in four corner areas of the rectangular hole-configuring region, each of the holes has a diameter, and the diameter of the one portion of the holes is smaller than the diameter of the another portion of the holes.Type: ApplicationFiled: April 12, 2023Publication date: August 3, 2023Inventors: Yi-Yuan HUANG, Cheng-Yu TSAO, Cheng-Sheng LIN, Tsung-Wei CHANG, Yi-Cheng LIU
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Patent number: 11271493Abstract: A rectifying bridge has a thyristor coupled in series with a rectifying element between a first rectified output terminal of a rectifying bridge circuit and a second rectified output terminal of the rectifying bridge circuit. A diode is coupled in series with a DC voltage source between a gate of the thyristor and the second rectified output terminal.Type: GrantFiled: June 10, 2020Date of Patent: March 8, 2022Assignee: STMicroelectronics LTDInventors: Laurent Gonthier, Yu Tsao Lin
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Publication number: 20210397927Abstract: A neural network system includes at least one memory and at least one processor. The memory is configured to store a front-end neural network, an encoding neural network, a decoding neural network and a back-end neural network. The processor is configured to execute the front-end neural network, the encoding neural network, the decoding neural network and the back-end neural network in the memory to perform operations including: utilizing the front-end neural network to output feature data; utilizing the encoding neural network to compress the feature data, and output compressed data which correspond to the feature data; utilizing the decoding neural network to decompress the compressed data, and output decompressed data which correspond to the feature data; and utilizing the back-end neural network to perform corresponding operations based on the decompressed data. A method of operating a neural network system is also disclosed herein.Type: ApplicationFiled: June 17, 2021Publication date: December 23, 2021Inventors: Yu-Ta CHEN, Feng-Ming LIANG, Shao-Yi CHIEN, Yu TSAO, Chen-En JIANG
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Patent number: 10978091Abstract: A system is provided to realize suppression by selecting wavelets for feature compression in distributed speech recognition. The system comprises a first device and a second device. The first device comprising: a first network module for connecting to a network; an acoustic transducer module for recording speech and outputting frames of recorded signal; and a first processor configured for the following: extracting multiple-dimensional speech features from the frames of the recorded signal to generate multiple feature sequences; applying discrete wavelet transform (DWT) to the feature sequences to obtain a plurality of component data; and transmitting at least one of the plurality of component data via the network, wherein another one of the plurality of component data is not transmitted.Type: GrantFiled: November 30, 2018Date of Patent: April 13, 2021Assignee: ACADEMIA SINICAInventors: Yu Tsao, Syu-Siang Wang
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Publication number: 20200395866Abstract: A rectifying bridge has a thyristor coupled in series with a rectifying element between a first rectified output terminal of a rectifying bridge circuit and a second rectified output terminal of the rectifying bridge circuit. A diode is coupled in series with a DC voltage source between a gate of the thyristor and the second rectified output terminal.Type: ApplicationFiled: June 10, 2020Publication date: December 17, 2020Inventors: Laurent GONTHIER, Yu Tsao LIN
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Publication number: 20190287551Abstract: A system is provided to realize suppression by selecting wavelets for feature compression in distributed speech recognition. The system comprises a first device and a second device. The first device comprising: a first network module for connecting to a network; an acoustic transducer module for recording speech and outputting frames of recorded signal; and a first processor configured for the following: extracting multiple-dimensional speech features from the frames of the recorded signal to generate multiple feature sequences; applying discrete wavelet transform (DWT) to the feature sequences to obtain a plurality of component data; and transmitting at least one of the plurality of component data via the network, wherein another one of the plurality of component data is not transmitted.Type: ApplicationFiled: November 30, 2018Publication date: September 19, 2019Inventors: Yu TSAO, SYU-SIANG WANG
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Patent number: 9763005Abstract: The present disclosure illustrates an acoustic echo cancellation method and system using the same. The acoustic echo cancellation method comprises the following steps. Firstly, a prior-knowledge matrix comprising a plurality of space vectors is built. Then, an initial filter vector is generated by the prior-knowledge matrix and an initial weighting vector. The weighting vector is updated based on the difference of the echo signal and the estimated signal in an iteration algorithm, and the coefficient of the filter vector is updated according to the updated weighting vector. An estimated signal is generated according to the updated filter vector and the original signal. Finally, the next echo signal is cancelled by the near-end estimated signal.Type: GrantFiled: October 29, 2014Date of Patent: September 12, 2017Assignee: YUAN ZE UNIVERSITYInventors: Yu Tsao, Shih Hau Fang, Yao Shiao, Yu-Cheng Su, Ying-Ren Chien
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Patent number: 9687208Abstract: A system for recognizing physiological sound comprises a receiving module, a feature extracting module, a classifier, and a comparing module. A method for recognizing physiological sound comprises receiving a physiological sound by the receiving module; extracting at least one feature from the physiological sound by the feature extraction module; classifying the at least one feature to identify at least one category by a classifier; and comparing the at least one category with a normal physiological sound and/or an abnormal physiological sound by the comparing module for evaluating a risk of disease. The method and system for recognizing physiological sound can precisely identify the specific physiological sound and exclude the noise.Type: GrantFiled: June 3, 2015Date of Patent: June 27, 2017Assignee: IMEDI PLUS Inc.Inventors: Kun-Hsi Tsai, Yu Tsao, Shih-Hsuan Ku, Tzu-Chen Liang, Yun-Fan Chang, Shih-I Yang
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Publication number: 20170056654Abstract: A signal processing method in cochlear implant is performed by a speech processor and comprises a noise reduction stage and a signal compression stage. The noise reduction stage can efficiently reduce noise in a electrical speech signal of a normal speech. The signal compression stage can perform good signal compression to enhance signals to stimulate cochlear nerves of a hearing loss patient. The patient who uses a cochlear implant performing the signal processing method of the present invention can understand normal speech.Type: ApplicationFiled: August 27, 2015Publication date: March 2, 2017Applicant: IMEDIPLUS INC.Inventors: Kun Hsi TSAI, Yu TSAO, Ying Hui LAI, Shih Hsuan KU
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Publication number: 20160354053Abstract: A system for recognizing physiological sound comprises a receiving module, a feature extracting module, a classifier, and a comparing module. A method for recognizing physiological sound comprises receiving a physiological sound by the receiving module; extracting at least one feature from the physiological sound by the feature extraction module; classifying the at least one feature to identify at least one category by a classifier; and comparing the at least one category with a normal physiological sound and/or an abnormal physiological sound by the comparing module for evaluating a risk of disease. The method and system for recognizing physiological sound can precisely identify the specific physiological sound and exclude the noise.Type: ApplicationFiled: June 3, 2015Publication date: December 8, 2016Inventors: Kun-Hsi TSAI, Yu TSAO, Shih-Hsuan KU, Tzu-Chen LIANG, Yun-Fan CHANG, Shih-I YANG
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Publication number: 20160057534Abstract: The present disclosure illustrates an acoustic echo cancellation method and system using the same. The acoustic echo cancellation method comprises the following steps. Firstly, a prior-knowledge matrix comprising a plurality of space vectors is built. Then, an initial filter vector is generated by the prior-knowledge matrix and an initial weighting vector. The weighting vector is updated based on the difference of the echo signal and the estimated signal in an iteration algorithm, and the coefficient of the filter vector is updated according to the updated weighting vector. An estimated signal is generated according to the updated filter vector and the original signal. Finally, the next echo signal is cancelled by the near-end estimated signal.Type: ApplicationFiled: October 29, 2014Publication date: February 25, 2016Inventors: YU TSAO, SHIH HAU FANG, YAO SHIAO, YU-CHENG SU, YING-REN CHIEN
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Patent number: 8744796Abstract: The present invention discloses an algorithm integrating system and an integrating method thereof. The algorithm integrating system comprises a receiving module, an analyzing module, and a processing module. The receiving module receives at least one test algorithm. The analyzing module is connected to the receiving module and analyzes the at least one test algorithm to obtain at least one basic element from the at least one test algorithm. The processing module is connected to the analyzing module and screen out the at least one non-duplicate basic element based on the at least one basic element. Then, the processing module integrates the at least one non-duplicate basic element and generates a testing module.Type: GrantFiled: April 18, 2011Date of Patent: June 3, 2014Assignee: HOY Technologies Co., Ltd.Inventors: Chun-Chia Chen, Li-Ming Teng, Yu-Tsao Hsing