Abstract: The present disclosure provides a method and an apparatus for testing a semiconductor device. The method includes providing an active area in an integrated circuit design layout; grouping the active area into a first region and a second region; calculating a first self-heating temperature of the first region of the active area; calculating a second self-heating temperature of the second region of the active area; and determining an Electromigration (EM) evaluation based on the first self-heating temperature and the second self-heating temperature.

Abstract: A series-connected absorption high-gravity device includes a housing, a rotating bed unit, a rotating shaft connected to the rotating bed unit, a scrubber layer, a blocking plate unit, and a guiding tube. The rotatable bed unit is disposed in the housing and defines a fluid-flowing space therein. The scrubber layer is disposed in the housing, is disposed above and spaced apart from the rotating bed unit, and cooperates with the rotating bed unit to define an airflow space therebetween. The blocking plate unit is disposed in the airflow space and includes a top blocking plate and a bottom blocking plate formed with a bottom through hole. The bottom through hole has a projection area along an axis of the rotating shaft smaller than a projection area of the top blocking plate and falling entirely therewithin. The guiding tube introduces a fluid into the fluid-flowing space.

Abstract: A method includes conducting an electromigration (EM) check process on a schematic design, conducting a mitigating process to mitigate one or more electromigration violations identified during conducting the EM check process, and generating a layout design of the schematic design after at least one iteration of a design process including the EM check process and the mitigating process. The EM check process includes selecting at least some circuits in the schematic design as selected circuits for electromigration check, and checking electromigration compliance in the selected circuits. The mitigating process includes one of modifying some circuit layout of the selected circuits, modifying the schematic design, or modifying both the schematic design and some circuit layout of the selected circuits.

Abstract: An insulation resistance detection system for an electric vehicle is used to detect a positive insulation resistance between a positive electrode of a battery of the electric vehicle and an equipment grounding point, and detect a negative insulation resistance between a negative electrode of the battery and the equipment grounding point. The insulation resistance detection system includes a negative detection circuit, a positive detection circuit, and a control unit. The control unit controls the negative detection circuit to be charged to generate a first capacitor voltage, and controls the positive detection circuit to be charged to generate a second capacitor voltage. The control unit determines whether the negative insulation resistance is abnormal according to the first capacitor voltage and a battery voltage of the battery, and determines whether the positive insulation resistance is abnormal according to the second capacitor voltage and the battery voltage.

Abstract: According to some embodiments of the disclosure, a semiconductor structure includes a first alignment region defined in a substrate layer and a first frame at edges of the first alignment region. A first alignment mark is in the first alignment region and bordered by the first frame. According to some embodiments of the disclosure, a method of fabricating a semiconductor structure includes forming an isolation structure over a substrate layer in a first alignment region. A process layer is formed over the isolation structure. A patterned mask is formed over the process layer. The process layer is patterned using the patterned mask as a template to form a first frame at edges of the first alignment region and a first alignment mark in the first alignment region and bordered by the first frame.

Abstract: An electromigration (EM) sign-off methodology that utilizes a system for analyzing an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes a memory and a processor configured for calculating adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat dissipating elements located within a defined thermal coupling volume or range of the heat sensitive structures.

Abstract: The present disclosure provides a method and an apparatus for testing a semiconductor device. The method includes providing an active area in an integrated circuit design layout; grouping the active area into a plurality of regions, each of the regions including at least one polysilicon gate; calculating an operating temperature of the at least one polysilicon gate in each of the regions; calculating a self-heating temperature of each of the regions based on the operating temperature of the at least one polysilicon gate in each of the regions; determining an Electromigration (EM) evaluation based on the self-heating temperatures of the regions; and generating a semiconductor device based on the integrated circuit design layout passing the EM evaluation, wherein one of the regions includes a number of polysilicon gates disposed thereon different from the number of polysilicon gates disposed on the rest of regions.

Abstract: A system including computer readable storage media including executable instructions and one or more processors configured to execute the executable instructions to obtain a schematic netlist and a performance specification for an integrated circuit, determine electrical constraints for nets in the schematic netlist based on the performance specification, determine physical constraints from the electrical constraints, rout the nets in the schematic netlist based on the electrical constraints and the physical constraints, and provide a data file of a layout.

Abstract: A wireless earphone with radar capabilities includes a first earphone having a first detection unit and a container. When the first earphone is placed inside the container, a first detection wave generated by the first detection unit passes through the container. The first detection wave is reflected from a human body as a first reflected wave, and when the first detection unit receives the first reflected wave through the container, the first detection unit generates a first detection result data and sends the first detection result data to an external device. The container containing the first earphone allows a user to hold the container with the first earphone within, and since the first earphone continues to detect movements outside of the container, the container is transformed into a multifunctional controller or detector for adapting to new application modes initiated by the external device.

Abstract: Disclosed is a CMOS image sensor with global shutters and a method for fabricating the CMOS image sensor. In one embodiment, a semiconductor device, includes: a light-sensing region; a charge-storage region; a light-shielding structure; and at least one via contact; wherein the charge-storage region is spatially configured adjacent to the light-sensing region in a lateral direction, wherein the light-shielding structure is configured over the charge-storage region in a vertical direction so as to prevent incident light leaking from the light-sensing region to the signal-processing region, wherein the light-shielding structure is configured in an interlayer dielectric (ILD) layer, and wherein the light-shielding structure is simultaneously formed with the at least one via contact.

Abstract: Air curtain devices can reduce defects on semiconductor wafers when implemented on a track equipped with robotic wafer transport. The air curtain devices can be added to one or more processing devices arranged along the track to prevent defects from landing on wafer surfaces. For example, the air curtain devices can prevent volatile organic solvent mist from drifting towards processing devices on the track and preventing contamination via a wafer transport system.

Abstract: A system for evaluating a heat sensitive structure of an integrated circuit design including a memory for retrieving and storing integrated circuit design layout data, thermal data, process data, and one or more operational parameters, a processor capable of accessing the memory and identifying a target region having a nominal temperature Tnom, a plurality of heat generating structures and/or heat dissipating structures having corresponding impact areas that encompass a portion of the target region, calculating the temperature increases and/or decreases in the target region as a result of thermal coupling between the target region and the heat generating structures and/or heat dissipating structures, and conducting one or more parametric evaluations of the target region at an adjusted evaluation temperature TE after which a network interface transmits the result(s) of the parametric evaluation(s) for use in a design review.

Abstract: An electromigration (EM) sign-off methodology that utilizes a system for analyzing an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes a memory and a processor configured for calculating adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat dissipating elements located within a defined thermal coupling volume or range of the heat sensitive structures.

Abstract: Disclosed is a CMOS image sensor with global shutters and a method for fabricating the CMOS image sensor. In one embodiment, a semiconductor device, includes: a light-sensing region; a charge-storage region; a light-shielding structure; and at least one via contact; wherein the charge-storage region is spatially configured adjacent to the light-sensing region in a lateral direction, wherein the light-shielding structure is configured over the charge-storage region in a vertical direction so as to prevent incident light leaking from the light-sensing region to the signal-processing region, wherein the light-shielding structure is configured in an interlayer dielectric (ILD) layer, and wherein the light-shielding structure is simultaneously formed with the at least one via contact.

Abstract: A system including computer readable storage media including executable instructions and one or more processors configured to execute the executable instructions to obtain a schematic netlist and a performance specification for an integrated circuit, determine electrical constraints for nets in the schematic netlist based on the performance specification, determine physical constraints from the electrical constraints, rout the nets in the schematic netlist based on the electrical constraints and the physical constraints, and provide a data file of a layout.

Abstract: Air curtain devices can reduce defects on semiconductor wafers when implemented on a track equipped with robotic wafer transport. The air curtain devices can be added to one or more processing devices arranged along the track to prevent defects from landing on wafer surfaces. For example, the air curtain devices can prevent volatile organic solvent mist from drifting towards processing devices on the track and preventing contamination via a wafer transport system.

Abstract: A vehicle floor mat includes a mat body and a liquid absorbing component. The mat body has a liquid cut off area. The liquid absorbing component is assembled with the mat body in a detachable manner. The liquid absorbing component includes a first liquid absorbing layer and a liquid isolating layer. The liquid isolating layer is disposed on the first liquid absorbing layer. The first liquid absorbing layer being adapted to cover the liquid cut off area, and the liquid isolating layer being a treading area of the vehicle floor mat. The mat body is a flat floor mat made of hydrophobic material, or a three dimensional floor mat made of the hydrophobic material.

Abstract: A system for evaluating a heat sensitive structure of an integrated circuit design including a memory for retrieving and storing integrated circuit design layout data, thermal data, process data, and one or more operational parameters, a processor capable of accessing the memory and identifying a target region having a nominal temperature Tnom, first and second heat generating structures within a first impact range of the target region, calculating the temperature increases ?Th1 and ?Th2 in the target region as a result of thermal coupling between the target region and the first and second heat generating structures, and conducting one or more parametric evaluations of the target region at an adjusted evaluation temperature TE=Tnom+?Th1+?Th1 after which a network interface transmits the result(s) of the parametric evaluation(s) for use in a design review.