Patents by Inventor Yu-Tsung Lai

Yu-Tsung Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210063869
    Abstract: A photomask includes a substrate, a multilayer stack disposed over the substrate and configured to reflect a radiation, a capping layer over the multilayer stack, and an anti-reflective layer over the capping layer. The anti-reflective layer comprises a first pattern, wherein the first pattern exposes the capping layer and is configured as a printable feature. The photomask also includes an absorber spaced apart from the printable feature from a top-view perspective.
    Type: Application
    Filed: April 15, 2020
    Publication date: March 4, 2021
    Inventors: CHIEN-HUNG LAI, HAO-MING CHANG, CHIA-SHIH LIN, HSUAN-WEN WANG, YU-HSIN HSU, CHIH-TSUNG SHIH, YU-HSUN WU
  • Publication number: 20210057637
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a cap layer on the first MTJ and the second MTJ; forming a passivation layer on the cap layer; removing part of the passivation layer to form a recess between the first MTJ and the second MTJ; forming an anti-reflective layer on the passivation layer and filling the recess; and removing the anti-reflective layer, the passivation layer, and the cap layer to form a first contact hole.
    Type: Application
    Filed: September 19, 2019
    Publication date: February 25, 2021
    Inventors: Chih-Wei Kuo, Chia-Chang Hsu, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Patent number: 10910553
    Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: February 2, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, Jun Xie
  • Publication number: 20210028352
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming an etch stop layer on the first IMD layer; forming a second IMD layer on the etch stop layer; forming a patterned hard mask on the second IMD layer; performing a first etching process to form a contact hole in the second IMD layer for exposing the etch stop layer; performing a second etching process to remove the patterned hard mask; performing a third etching process to remove the etch stop layer and the first IMD layer for exposing the MTJ; and forming a metal interconnection in the contact hole.
    Type: Application
    Filed: October 7, 2020
    Publication date: January 28, 2021
    Inventors: Chih-Wei Kuo, Meng-Jun Wang, Yi-Wei Tseng, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Patent number: 10903269
    Abstract: A magnetic memory device includes a first dielectric layer on a substrate, first and second via plugs in the first dielectric layer, first and second cylindrical memory stacks on the first and second via plugs, respectively, and an insulating cap layer conformally disposed on the first dielectric layer and on sidewalls of the first and second cylindrical memory stacks. The insulating cap layer is not disposed in a logic area and a via forming region between the first and second cylindrical memory stacks.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: January 26, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Publication number: 20210020693
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a passivation layer on the first MTJ and the second MTJ; removing part of the passivation layer so that a top surface of all of the remaining passivation layer is lower than a top surface of the first electrode; and forming a ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ.
    Type: Application
    Filed: August 20, 2019
    Publication date: January 21, 2021
    Inventors: Chih-Wei Kuo, Tai-Cheng Hou, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Publication number: 20210020828
    Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
    Type: Application
    Filed: August 5, 2019
    Publication date: January 21, 2021
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, JUN XIE
  • Publication number: 20210013395
    Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a metal interconnection. The two magnetic tunnel junction elements are arranged side by side at a first direction. The metal interconnection is disposed between the magnetic tunnel junction elements, wherein the metal interconnection includes a contact plug part having a long shape at a top view, and the long shape has a length at a second direction larger than a width at the first direction, wherein the second direction is orthogonal to the first direction.
    Type: Application
    Filed: August 1, 2019
    Publication date: January 14, 2021
    Inventors: Chih-Wei Kuo, Ting-Hsiang Huang, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Publication number: 20200388648
    Abstract: A magnetic memory device includes a first dielectric layer on a substrate, first and second via plugs in the first dielectric layer, first and second cylindrical memory stacks on the first and second via plugs, respectively, and an insulating cap layer conformally disposed on the first dielectric layer and on sidewalls of the first and second cylindrical memory stacks. The insulating cap layer is not disposed in a logic area and a via forming region between the first and second cylindrical memory stacks.
    Type: Application
    Filed: July 8, 2019
    Publication date: December 10, 2020
    Inventors: Chih-Wei Kuo, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Publication number: 20200373479
    Abstract: A semiconductor device includes: a magnetic tunneling junction (MTJ) on a substrate; a first inter-metal dielectric (IMD) layer around the MTJ; a metal interconnection on and directly contacting the MTJ; a second IMD layer on the first IMD layer and around the metal interconnection; and a metal oxide layer on the second IMD layer and around the metal interconnection.
    Type: Application
    Filed: June 13, 2019
    Publication date: November 26, 2020
    Inventors: Chih-Wei Kuo, Meng-Jun Wang, Yi-Wei Tseng, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Patent number: 10847709
    Abstract: A semiconductor device includes: a magnetic tunneling junction (MTJ) on a substrate; a first inter-metal dielectric (IMD) layer around the MTJ; a metal interconnection on and directly contacting the MTJ; a second IMD layer on the first IMD layer and around the metal interconnection; and a metal oxide layer on the second IMD layer and around the metal interconnection.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: November 24, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Meng-Jun Wang, Yi-Wei Tseng, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Patent number: 10804138
    Abstract: A method for fabricating a semiconductor device includes the steps of: providing a first dielectric layer having a metal layer therein; forming a second dielectric layer on the first dielectric layer and the metal layer; forming a metal oxide layer on the second dielectric layer; performing a first etching process by using a chlorine-based etchant to remove part of the metal oxide layer to forma via opening and expose the second dielectric layer; forming a block layer on sidewalls of the metal oxide layer and a top surface of the second dielectric layer; and performing a second etching process by using a fluorine-based etchant to remove part of the block layer and part of the second dielectric layer for exposing a top surface of the metal layer.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: October 13, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Patent number: 10743926
    Abstract: An osteo-implant including two end portions, at least one middle structure, and a plurality of connection portions is provided. The middle structure is disposed between the two end portions and includes a plurality of middle portions. The middle portions are connected to the two end portions through the connection portions. When the two end portions are moved relatively along an axial direction of the osteo-implant, the two end portions drive the middle portions to push with each other and have displacements along a radial direction of the osteo-implant through the connection portions, such that an outer diameter of the osteo-implant is increased by the middle portions.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: August 18, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Jun Li, Hong-Jen Lai, Pei-I Tsai, Fang-Hei Tsau, Wei-Chin Huang, Yu-Tsung Chiu
  • Patent number: 10699913
    Abstract: Exemplary metal line structure and manufacturing method for a trench are provided. In particular, the metal line structure includes a substrate, a target layer, a trench and a conductor line. The target layer is formed on the substrate. The trench is formed in the target layer and has a micro-trench formed at the bottom thereof. A depth of the micro-trench is not more than 50 angstroms. The conductor line is inlaid into the trench.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: June 30, 2020
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Shin-Chi Chen, Jiunn-Hsiung Liao, Yu-Tsung Lai
  • Publication number: 20200197059
    Abstract: An osteo-implant including two end portions, at least one middle structure, and a plurality of connection portions is provided. The middle structure is disposed between the two end portions and includes a plurality of middle portions. The middle portions are connected to the two end portions through the connection portions. When the two end portions are moved relatively along an axial direction of the osteo-implant, the two end portions drive the middle portions to push with each other and have displacements along a radial direction of the osteo-implant through the connection portions, such that an outer diameter of the osteo-implant is increased by the middle portions.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 25, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Ming-Jun Li, Hong-Jen Lai, Pei-I Tsai, Fang-Hei Tsau, Wei-Chin Huang, Yu-Tsung Chiu
  • Patent number: 10636744
    Abstract: A memory device includes an insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, a connection hole disposed on the interconnection structure and penetrates the dielectric layer, an alignment mark trench penetrating the dielectric layer on a peripheral region, a first patterned conductive layer, and a patterned memory material layer. The first patterned conductive layer includes a connection structure at least partly disposed in the connection hole and a first pattern disposed in the alignment mark trench. The patterned memory material layer includes a first memory material pattern disposed on the connection structure and a second memory material pattern disposed in the alignment mark trench. Manufacturing yield and alignment condition of forming the memory device may be improved by disposing a part of the first patterned conductive layer in the alignment mark trench.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: April 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Meng-Jun Wang, Jiunn-Hsiung Liao, Yu-Tsung Lai
  • Publication number: 20200051922
    Abstract: A memory device includes an insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, a connection hole disposed on the interconnection structure and penetrates the dielectric layer, an alignment mark trench penetrating the dielectric layer on a peripheral region, a first patterned conductive layer, and a patterned memory material layer. The first patterned conductive layer includes a connection structure at least partly disposed in the connection hole and a first pattern disposed in the alignment mark trench. The patterned memory material layer includes a first memory material pattern disposed on the connection structure and a second memory material pattern disposed in the alignment mark trench. Manufacturing yield and alignment condition of forming the memory device may be improved by disposing a part of the first patterned conductive layer in the alignment mark trench.
    Type: Application
    Filed: August 9, 2018
    Publication date: February 13, 2020
    Inventors: Meng-Jun Wang, Jiunn-Hsiung Liao, Yu-Tsung Lai
  • Patent number: 10341471
    Abstract: A packet analysis apparatus, method, and non-transitory computer readable medium thereof are provided. The packet analysis apparatus stores a plurality of packets whose formats are unknown. The packet analysis apparatus calculates a plurality of cross-correlation values of the packets. The packet analysis apparatus decides at least one group according to the cross-correlation values and at least one first threshold, wherein each group includes a subset of the packets. The packets included in a specific group of the groups define a plurality of bit positions. Each packet included in the specific group has a plurality of bits. For each of the bit positions, the packet analysis apparatus calculates a variation degree of the bits corresponding to the bit positions. The packet analysis apparatus selects the at least one bit position whose variation degree(s) is/are smaller than a second threshold as at least one field boundary of the specific group.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: July 2, 2019
    Assignee: ONWARD SECURITY CORPORATION
    Inventors: Chao Yeh Lai, Chien Tsung Liu, Yu Chieh Li
  • Publication number: 20190160772
    Abstract: A protective structure is provided, which includes a porous layer and a surface layer disposed on the porous layer. The porous layer includes a first copolymer, a plurality of pores, and a plurality of first silica particles, wherein the first copolymer is polymerized from a first monomer composition. The first monomer composition includes N,N-dimethylacrylamide and N-vinylpyrrolidone. The surface layer includes a second copolymer, a plurality of fibers, and a plurality of second silica particles, wherein the second copolymer is polymerized from a second monomer composition. The second monomer composition includes N,N-dimethylacrylamide and N-vinylpyrrolidone.
    Type: Application
    Filed: December 22, 2017
    Publication date: May 30, 2019
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jiun-You LIOU, Tsao-Ming PENG, Shih-Ming CHEN, Wei-Hao LAI, Yu-Tsung CHIU
  • Publication number: 20190131142
    Abstract: Exemplary metal line structure and manufacturing method for a trench are provided. In particular, the metal line structure includes a substrate, a target layer, a trench and a conductor line. The target layer is formed on the substrate. The trench is formed in the target layer and has a micro-trench formed at the bottom thereof. A depth of the micro-trench is not more than 50 angstroms. The conductor line is inlaid into the trench.
    Type: Application
    Filed: December 13, 2018
    Publication date: May 2, 2019
    Inventors: Shin-Chi CHEN, Jiunn-Hsiung LIAO, Yu-Tsung LAI