Patents by Inventor Yu-Tsung Lai

Yu-Tsung Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240150354
    Abstract: The present application provides tricyclic urea compounds that modulate the activity of the V617F variant of JAK2, which are useful in the treatment of various diseases, including cancer.
    Type: Application
    Filed: August 24, 2023
    Publication date: May 9, 2024
    Inventors: Yanran Ai, Onur Atasoylu, Yu Bai, Joseph Barbosa, David M. Burns, Daniel Levy, Brent Douty, Hao Feng, Leah C. Konkol, Cheng-Tsung Lai, Xun Liu, Song Mei, Jun Pan, Haisheng Wang, Liangxing Wu, Wenqing Yao, Eddy W. Yue
  • Publication number: 20240032439
    Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 25, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, JUN XIE
  • Publication number: 20230413579
    Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first top electrode on the first MTJ and a second top electrode on the second MTJ, a first spacer and a second spacer around the first MTJ, a third spacer and a fourth spacer around the second MTJ, a passivation layer between the second spacer and the third spacer as a top surface of the passivation layer includes a V-shape, and an ultra low-k (ULK) dielectric layer on the passivation layer and around the first MTJ and the second MTJ.
    Type: Application
    Filed: September 5, 2023
    Publication date: December 21, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Tai-Cheng Hou, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Publication number: 20230403946
    Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.
    Type: Application
    Filed: August 28, 2023
    Publication date: December 14, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Laio, Yu-Tsung Lai, Wei-Hao Huang
  • Patent number: 11812669
    Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, a top electrode layer on the magnetic tunnel junction stack, and a hard mask layer on said top electrode layer, wherein the material of top electrode layer is titanium nitride, a material of said hard mask layer is tantalum or tantalum nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: November 7, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, Jun Xie
  • Publication number: 20230354715
    Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.
    Type: Application
    Filed: June 27, 2023
    Publication date: November 2, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Patent number: 11785785
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a passivation layer on the first MTJ and the second MTJ; removing part of the passivation layer so that a top surface of all of the remaining passivation layer is lower than a top surface of the first electrode; and forming a ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: October 10, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Tai-Cheng Hou, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Publication number: 20230320229
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and form a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.
    Type: Application
    Filed: May 10, 2023
    Publication date: October 5, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Patent number: 11778922
    Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: October 3, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Patent number: 11737370
    Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: August 22, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Patent number: 11706993
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.
    Type: Grant
    Filed: December 27, 2020
    Date of Patent: July 18, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Patent number: 11545522
    Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first top electrode on the first MTJ and a second top electrode on the second MTJ, a passivation layer between the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on and directly contacting the passivation layer and around the first MTJ and the second MTJ. Preferably, a top surface of the passivation layer includes a V-shape and a valley point of the V-shape is higher than a bottom surface of the first top electrode.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: January 3, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Tai-Cheng Hou, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Publication number: 20220302374
    Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, a top electrode layer on the magnetic tunnel junction stack, and a hard mask layer on said top electrode layer, wherein the material of top electrode layer is titanium nitride, a material of said hard mask layer is tantalum or tantalum nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
    Type: Application
    Filed: June 9, 2022
    Publication date: September 22, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, JUN XIE
  • Patent number: 11387408
    Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: July 12, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, Jun Xie
  • Patent number: 11283007
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming an etch stop layer on the first IMD layer; forming a second IMD layer on the etch stop layer; forming a patterned hard mask on the second IMD layer; performing a first etching process to form a contact hole in the second IMD layer for exposing the etch stop layer; performing a second etching process to remove the patterned hard mask; performing a third etching process to remove the etch stop layer and the first IMD layer for exposing the MTJ; and forming a metal interconnection in the contact hole.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: March 22, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Meng-Jun Wang, Yi-Wei Tseng, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Publication number: 20220085283
    Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.
    Type: Application
    Filed: November 22, 2021
    Publication date: March 17, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Patent number: 11271154
    Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a metal interconnection. The two magnetic tunnel junction elements are arranged side by side at a first direction. The metal interconnection is disposed between the magnetic tunnel junction elements, wherein the metal interconnection includes a contact plug part having a long shape at a top view, and the long shape has a length at a second direction larger than a width at the first direction, wherein the second direction is orthogonal to the first direction.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: March 8, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Ting-Hsiang Huang, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Publication number: 20210296576
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a passivation layer on the first MTJ and the second MTJ; removing part of the passivation layer so that a top surface of all of the remaining passivation layer is lower than a top surface of the first electrode; and forming a ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ.
    Type: Application
    Filed: June 1, 2021
    Publication date: September 23, 2021
    Inventors: Chih-Wei Kuo, Tai-Cheng Hou, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Publication number: 20210288107
    Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first top electrode on the first MTJ and a second top electrode on the second MTJ, a passivation layer between the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on and directly contacting the passivation layer and around the first MTJ and the second MTJ. Preferably, a top surface of the passivation layer includes a V-shape and a valley point of the V-shape is higher than a bottom surface of the first top electrode.
    Type: Application
    Filed: June 1, 2021
    Publication date: September 16, 2021
    Inventors: Chih-Wei Kuo, Tai-Cheng Hou, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Patent number: 11121307
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a cap layer on the first MTJ and the second MTJ; forming a passivation layer on the cap layer; removing part of the passivation layer to form a recess between the first MTJ and the second MTJ; forming an anti-reflective layer on the passivation layer and filling the recess; and removing the anti-reflective layer, the passivation layer, and the cap layer to form a first contact hole.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: September 14, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Chia-Chang Hsu, Yu-Tsung Lai, Jiunn-Hsiung Liao