Patents by Inventor Yu Tung Chen

Yu Tung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240385507
    Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
  • Patent number: 12124163
    Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
  • Publication number: 20240178112
    Abstract: A semiconductor package structure includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a passivation layer on the semiconductor substrate and the conductive pad. The passivation layer exposes a portion of the top surface of the conductive pad. The semiconductor package structure also includes a conductive adhesive layer on the conductive pad, and a dielectric layer on the passivation layer and the conductive adhesive layer. The dielectric layer exposes a portion of the conductive adhesive layer. The semiconductor package structure also includes a redistribution layer (RDL) structure on the dielectric layer and electrically connected to the conductive pad through the conductive adhesive layer. The semiconductor package structure also includes a bump structure over the RDL structure.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 30, 2024
    Inventors: Yu-Tung CHEN, Kuo-Lung FAN, Yen-Yao CHI, Nai-Wei LIU, Pei-Haw TSAO
  • Publication number: 20240112963
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor wafer and a test structure. The semiconductor wafer has a substrate having a scribe line area, a first die area and a second die area. The first die area and the second die area are separated by the scribe line area extending along a first direction. The test structure is disposed in the scribe line area. The test structure includes a test device and a first test pad. The test device has a physical characteristic similar to a semiconductor device fabricated in the first die area or the second die area. The first test pad is electrically connected to the test device. A first distance between the first test pad and the first die area gradually increases from a center region to a peripheral region of the first test pad in the first direction.
    Type: Application
    Filed: August 8, 2023
    Publication date: April 4, 2024
    Inventors: Yu-Tung CHEN, Pei-Haw TSAO, Kuo-Lung FAN, Yuan-Fu CHUNG
  • Patent number: 11860530
    Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
  • Publication number: 20230386954
    Abstract: A wafer level chip scale package includes a bare silicon die having an active surface, a rear surface opposite to the active surface, and a sidewall surface between the active surface and the rear surface. The bare silicon die includes a backside corner between the rear surface and the sidewall surface. A plurality of pads is disposed on the active surface. A plurality of conductive elements is disposed on the plurality of pads, respectively. A backside tape is adhered to the rear surface by using an adhesive layer. The adhesive layer and the backside tape protrude beyond the sidewall surfaces of the bare silicon die. The adhesive layer extends along the sidewall surface and wraps around the backside corner.
    Type: Application
    Filed: April 10, 2023
    Publication date: November 30, 2023
    Applicant: MEDIATEK INC.
    Inventors: Yu-Tung Chen, Pei-Haw Tsao, Kuo-Lung Fan
  • Publication number: 20230367197
    Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
  • Publication number: 20230098788
    Abstract: A metal mesh structure includes at least one first wire extending along a first direction and at least one second wire extending along a second direction different from the first direction. The at least one first wire includes a first portion, a second portion and a first bending portion connected between the first portion and the second portion. The first bending portion crosses the at least one second wire to form a node. An extending line of the first portion along the first direction passes through the node and is overlapped with the second portion. A first included angle is included between the first direction and the second direction, and a second included angle is included between the first bending portion and the at least one second wire, wherein the first included angle is different from the second included angle, and the second included angle is 90 degrees.
    Type: Application
    Filed: March 21, 2022
    Publication date: March 30, 2023
    Applicant: HENGHAO TECHNOLOGY CO., LTD.
    Inventors: Yu-Tung Chen, Shan-Chen Huang, Yu-Yuan Yeh
  • Patent number: 11604552
    Abstract: A metal mesh structure includes at least one first wire extending along a first direction and at least one second wire extending along a second direction different from the first direction. The at least one first wire includes a first portion, a second portion and a first bending portion connected between the first portion and the second portion. The first bending portion crosses the at least one second wire to form a node. An extending line of the first portion along the first direction passes through the node and is overlapped with the second portion. A first included angle is included between the first direction and the second direction, and a second included angle is included between the first bending portion and the at least one second wire, wherein the first included angle is different from the second included angle, and the second included angle is 90 degrees.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: March 14, 2023
    Assignee: HENGHAO TECHNOLOGY CO., LTD.
    Inventors: Yu-Tung Chen, Shan-Chen Huang, Yu-Yuan Yeh
  • Publication number: 20220350235
    Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
    Type: Application
    Filed: June 30, 2022
    Publication date: November 3, 2022
    Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
  • Patent number: 11402743
    Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
  • Publication number: 20220066312
    Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
    Type: Application
    Filed: August 31, 2020
    Publication date: March 3, 2022
    Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
  • Patent number: 10388541
    Abstract: A wafer coating system includes a wafer chuck, a flowing insulating material sprayer and a wafer tilting lifting pin. The wafer chuck has a carrier part and a rotating part, which the carrier part is mounted on the rotating part to carry a wafer, and the rotating part is configured to rotate with a predetermined axis. The flowing insulating material sprayer is above the wafer chuck and configured to spray a flowing insulating material to the wafer, and the wafer tilting lifting pin is configured to form a first acute angle between the wafer and direction of gravity.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: August 20, 2019
    Assignee: XINTEC INC.
    Inventors: Yu-Tung Chen, Quan-Qun Su, Chuan-Jin Shiu, Chien-Hui Chen, Hsiao-Lan Yeh, Yen-Shih Ho
  • Publication number: 20180284327
    Abstract: An anti-glare wear-resistant cover plate including a cover plate body is provided. The cover plate body has a plurality of microstructures located at an anti-glare side of the cover plate body. The plurality of microstructures has a plurality of top surfaces, wherein a change in slope of a section line of each of the plurality of top surfaces on a reference plane perpendicular to the cover plate body is continuous. A manufacturing method of the anti-glare wear-resistant cover plate is also provided.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 4, 2018
    Applicant: HENGHAO TECHNOLOGY CO., LTD
    Inventors: Chun-Jung Chen, Yu-Tung Chen, Chin-Chang Liu
  • Patent number: 9613904
    Abstract: A semiconductor structure includes a first substrate, a second substrate, a dam layer, a photoresist layer, and a conductive layer. The first substrate has a conductive pad. The second substrate has a through via, a sidewall surface surrounding the through via, a first surface, and a second surface opposite to the first surface. The through via penetrates through the first and second surfaces. The conductive pad is aligned with the through via. The dam layer is located between the first substrate and the second surface. The dam layer protrudes toward the through via. The photoresist layer is located on the first surface, the sidewall surface, the dam layer protruding toward the through via, and between the conductive pad and the dam layer protruding toward the through via. The conductive layer is located on the photoresist layer and the conductive pad.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: April 4, 2017
    Assignee: XINTEC INC.
    Inventors: Yu-Tung Chen, Chien-Min Lin, Chuan-Jin Shiu, Chih-Wei Ho, Yen-Shih Ho
  • Publication number: 20160329283
    Abstract: A semiconductor structure includes a first substrate, a second substrate, a dam layer, a photoresist layer, and a conductive layer. The first substrate has a conductive pad. The second substrate has a through via, a sidewall surface surrounding the through via, a first surface, and a second surface opposite to the first surface. The through via penetrates through the first and second surfaces. The conductive pad is aligned with the through via. The dam layer is located between the first substrate and the second surface. The dam layer protrudes toward the through via. The photoresist layer is located on the first surface, the sidewall surface, the dam layer protruding toward the through via, and between the conductive pad and the dam layer protruding toward the through via. The conductive layer is located on the photoresist layer and the conductive pad.
    Type: Application
    Filed: April 27, 2016
    Publication date: November 10, 2016
    Inventors: Yu-Tung CHEN, Chien-Min LIN, Chuan-Jin SHIU, Chih-Wei HO, Yen-Shih HO
  • Publication number: 20160307779
    Abstract: A wafer coating system includes a wafer chuck, a flowing insulating material sprayer and a wafer tilting lifting pin. The wafer chuck has a carrier part and a rotating part, which the carrier part is mounted on the rotating part to carry a wafer, and the rotating part is configured to rotate with a predetermined axis. The flowing insulating material sprayer is above the wafer chuck and configured to spray a flowing insulating material to the wafer, and the wafer tilting lifting pin is configured to form a first acute angle between the wafer and direction of gravity.
    Type: Application
    Filed: April 13, 2016
    Publication date: October 20, 2016
    Inventors: Yu-Tung CHEN, Quan-Qun SU, Chuan-Jin SHIU, Chien-Hui CHEN, Hsiao-Lan YEH, Yen-Shih HO
  • Publication number: 20160004434
    Abstract: An information input device includes a pressure sensing unit, a display unit and a processing unit. The pressure sensing unit senses an operating pressure at a at least one press-button point, and generates a signal of the at least one press-button point in a pressure arrangement state. The display unit provides a selection tool and a position target indicating the pressure arrangement state. The processing unit, according to the signal, causes the selection tool to select the position target, and generates an input information representing the pressure arrangement state.
    Type: Application
    Filed: July 1, 2015
    Publication date: January 7, 2016
    Inventors: Ming-Chuan Chih, Zhen-Yu Yang, Yu-Tung Chen
  • Patent number: 8159619
    Abstract: A multi-standard integrated television receiver is disclosed. According to the invention, a RF tracking filter is provided to receive a RF signal and then filter out a fifth order and above harmonics and a band-pass filter is provided to further eliminate harmonics. Moreover, a double quadrature mixer is provided to remove third order harmonics. Accordingly, the quality factor requirement of the RF tracking filter and the linearity requirement of the band-pass filter are relaxed. Thus, the RF tracking filter and the band-pass filter can be fully integrated without any external components.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: April 17, 2012
    Assignee: Sunplus Technology Co., Ltd.
    Inventor: Yu-Tung Chen
  • Publication number: 20100085490
    Abstract: A multi-standard integrated television receiver is disclosed. According to the invention, a RF tracking filter is provided to receive a RF signal and then filter out a fifth order and above harmonics and a band-pass filter is provided to further eliminate harmonics. Moreover, a double quadrature mixer is provided to remove third order harmonics. Accordingly, the quality factor requirement of the RF tracking filter and the linearity requirement of the band-pass filter are relaxed. Thus, the RF tracking filter and the band-pass filter can be fully integrated without any external components.
    Type: Application
    Filed: October 6, 2009
    Publication date: April 8, 2010
    Inventor: Yu-Tung CHEN