Patents by Inventor Yu-Wei Chiang

Yu-Wei Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240143888
    Abstract: An integrated circuit includes a first and second active region, a first insulating region, and a first and second contact. The first and second active region extend in a first direction, and are on a first level. The first active region includes a first and second drain/source region. The second active region includes a third drain/source region. The first insulating region is over the first drain/source region. The first contact overlaps the third drain/source region, is electrically coupled to the third drain/source region and is located on a second level. The second contact includes a first and second portion. The first portion overlaps the first and second drain/source. The second portion overlaps the first contact, the first and third drain/source region, and the first insulating region, and is electrically coupled to the first portion, and electrically insulated from the first drain/source region.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Inventors: Pochun WANG, Yu-Jung CHANG, Hui-Zhong ZHUANG, Ting-Wei CHIANG
  • Publication number: 20240136420
    Abstract: A thin film transistor includes a substrate, a semiconductor layer, a gate insulating layer, a gate, a source and a drain. The semiconductor layer is located above the substrate. The gate insulating layer is located above the semiconductor layer. The gate is located above the gate insulating layer and overlapping with the semiconductor layer. The gate includes a first portion, a second portion and a third portion. The first portion is extending along the surface of the gate insulating layer and directly in contact with the gate insulating layer. The second portion is separated from the gate insulating layer. Taking the surface of the gate insulating layer as a reference, the top surface of the second portion is higher than the top surface of the first portion. The third portion connects the first portion to the second portion. The source and the drain are electrically connected to the semiconductor layer.
    Type: Application
    Filed: December 1, 2022
    Publication date: April 25, 2024
    Applicant: AUO Corporation
    Inventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun
  • Patent number: 11956421
    Abstract: Method and apparatus of video coding are disclosed. According to one method, in the decoder side, a predefined Intra mode is assigned to a neighboring block adjacent to the current luma block when the neighboring block satisfies one or more conditions. An MPM (Most Probable Mode) list is derived based on information comprising at least one of neighboring Intra modes. A current Intra mode is derived utilizing the MPM list. The current luma block is decoded according to the current Intra mode According to another method, a predefined Intra mode is assigned to a neighboring block adjacent to the current luma block if the neighboring block is coded in BDPCM (Block-based Delta Pulse Code Modulation) mode, where the predefined Intra mode is set to horizontal mode or vertical mode depending on prediction direction used by the BDPCM mode.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: April 9, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Man-Shu Chiang, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang, Shih-Ta Hsiang
  • Publication number: 20240114690
    Abstract: A method of forming a three-dimensional (3D) memory device includes: forming, over a substrate, a layer stack having alternating layers of a first conductive material and a first dielectric material; forming trenches extending vertically through the layer stack from an upper surface of the layer stack distal from the substrate to a lower surface of the layer stack facing the substrate; lining sidewalls and bottoms of the trenches with a memory film; forming a channel material over the memory film, the channel material including an amorphous material; filling the trenches with a second dielectric material after forming the channel material; forming memory cell isolation regions in the second dielectric material; forming source lines (SLs) and bit lines (BLs) that extend vertically in the second dielectric material on opposing sides of the memory cell isolation regions; and crystallizing first portions of the channel material after forming the SLs and BLs.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: TsuChing Yang, Hung-Chang Sun, Kuo Chang Chiang, Sheng-Chih Lai, Yu-Wei Jiang
  • Patent number: 11935854
    Abstract: A method for forming a bonded semiconductor structure is disclosed. A first device wafer having a first bonding layer and a first bonding pad exposed from the first bonding layer and a second device wafer having a second bonding layer and a second bonding pad exposed from the second bonding layer are provided. Following, a portion of the first bonding pad is removed until a sidewall of the first bonding layer is exposed, and a portion of the second bonding layer is removed to expose a sidewall of the second bonding pad. The first device wafer and the second device wafer are then bonded to form a dielectric bonding interface between the first bonding layer and the second bonding layer and a conductive bonding interface between the first bonding pad and the second bonding pad. The conductive bonding interface and the dielectric bonding interface comprise a step-height.
    Type: Grant
    Filed: March 8, 2023
    Date of Patent: March 19, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Sung Chiang, Chia-Wei Liu, Yu-Ruei Chen, Yu-Hsiang Lin
  • Publication number: 20240088291
    Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chang Sun, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, TsuChing Yang, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20240071954
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20240071953
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Patent number: 11917185
    Abstract: A method and apparatus of Inter prediction for video coding using Multi-hypothesis (MH) are disclosed. If an MH mode is used for the current block: at least one MH candidate is derived using reduced reference data by adjusting at least one coding-control setting; an Inter candidate list is generated, where the Inter candidate list comprises said at least one MH candidate; and current motion information associated with the current block is encoded using the Inter candidate list at the video encoder side or the current motion information associated with the current block is decoded at the video decoder side using the Merge candidate list. The coding control setting may correspond to prediction direction setting, filter tap setting, block size of reference block to be fetched, reference picture setting or motion limitation setting.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: February 27, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Man-Shu Chiang, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang
  • Patent number: 10617752
    Abstract: The present invention relates to canine influenza virus strains, and vaccines and compositions. The present invention also relates to reagents and methods allowing their detection, methods of vaccination as well as methods of producing these reagents and vaccines.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: April 14, 2020
    Assignee: BOEHRINGER INGELHEIM ANIMAL HEALTH USA INC.
    Inventors: Yu-Wei Chiang, David Cureton, Herve Poulet
  • Publication number: 20180250382
    Abstract: The present invention relates to canine influenza virus strains, and vaccines and compositions. The present invention also relates to reagents and methods allowing their detection, methods of vaccination as well as methods of producing these reagents and vaccines.
    Type: Application
    Filed: June 23, 2016
    Publication date: September 6, 2018
    Applicant: MERIAL INC.
    Inventors: Yu-Wei Chiang, David Cureton, Herve Poulet
  • Patent number: 10010499
    Abstract: The present invention relates to microneedle vaccine formulations, as well as methods of use thereof to provide animals, including canines, protective immunity against infection and disease caused by rabies viruses. Once placed onto the skin of the animals, the microneedle formulations dissolve quickly into the surrounding skin, where the antigens then elicit in the animals high and protective levels of rabies virus neutralizing antibodies.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: July 3, 2018
    Assignees: MERIAL INC., Georgia Tech Research Corporation
    Inventors: Yu-Wei Chiang, Mark R. Prausnitz, Kristopher Daniel DeWitt, Jaya Arya
  • Patent number: 10010605
    Abstract: The present invention encompasses FMDV vaccines or compositions. The vaccine or composition may be a vaccine or composition containing FMDV antigens. The invention also encompasses recombinant vectors encoding and expressing FMDV antigens, epitopes or immunogens which can be used to protect animals, in particular ovines, bovines, caprines, or swines, against FMDV.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: July 3, 2018
    Assignee: Merial, Inc.
    Inventors: Jean-Christophe Audonnet, Zahia Hannas-Djebbara, Teshome Mebatsion, Yu-Wei Chiang, Justin Widener, Frédéric Reynard
  • Publication number: 20160220659
    Abstract: The present invention encompasses FMDV vaccines or compositions. The vaccine or composition may be a vaccine or composition containing FMDV antigens. The invention also encompasses recombinant vectors encoding and expressing FMDV antigens, epitopes or immunogens which can be used to protect animals, in particular ovines, bovines, caprines, or swines, against FMDV.
    Type: Application
    Filed: September 23, 2015
    Publication date: August 4, 2016
    Applicant: MERIAL, INC.
    Inventors: Jean-Christophe Audonnet, Zahia Hannas-Djebbara, Teshome Mebatsion, Yu-Wei Chiang, Justin Widener, Frédéric Reynard
  • Publication number: 20160120799
    Abstract: The present invention relates to microneedle vaccine formulations, as well as methods of use thereof to provide animals, including canines, protective immunity against infection and disease caused by rabies viruses. Once placed onto the skin of the animals, the microneedle formulations dissolve quickly into the surrounding skin, where the antigens then elicit in the animals high and protective levels of rabies virus neutralizing antibodies.
    Type: Application
    Filed: November 3, 2015
    Publication date: May 5, 2016
    Applicants: GEORGIA TECH RESEARCH CORPORATION, MERIAL, INC.
    Inventors: Yu-Wei Chiang, Mark R. Prausnitz, Kristopher Daniel DeWitt, Jaya Arya
  • Patent number: 7635481
    Abstract: The present invention provides a safe and effective vaccine composition which comprises: an effective immunizing amount of an inactivated Ehrlichia canis bacterin; a pharmacologically acceptable carrier; and an immunogenically stimulating amount of an adjuvant system consisting essentially of an antibody response inducing agent and a cell-mediated immunity response inducing agent. The present invention also provides a method for the prevention or amelioration of canine ehrlichiosis in dogs.
    Type: Grant
    Filed: April 20, 2006
    Date of Patent: December 22, 2009
    Assignee: Wyeth
    Inventors: Liangbiao (George) Hu, Thomas J. Hess, Yu-Wei Chiang, Hsien-Jue (Steve) Chu
  • Publication number: 20070092537
    Abstract: Compositions, including vaccine compositions, and methods for treating, preventing or ameliorating canine influenza virus (CIV) disease by utilizing one or more canine influenza virus (CIV) or equine influenza virus (EIV) strain or immunogens thereof are set forth herein. Also set forth are challenge models useful in assessing the efficacy of a composition against canine influenza virus, comprising an equine influenza virus (EIV) or canine influenza virus (CIV) strain or immunogens thereof.
    Type: Application
    Filed: October 18, 2006
    Publication date: April 26, 2007
    Applicant: Wyeth
    Inventors: Yu-Wei Chiang, Hsien-Jue Chu, Michael Gill, Kim Gugisberg
  • Publication number: 20060222660
    Abstract: A method, composition and kit for reducing or preventing immunogenic interference in a multi-valent vaccine utilizes a nucleic acid or DNA component along with other non-nucleic acid immunogenic components.
    Type: Application
    Filed: March 28, 2006
    Publication date: October 5, 2006
    Applicant: Wyeth
    Inventors: Hsien-Jue Chu, Yu-Wei Chiang, Terry Ng
  • Publication number: 20060188524
    Abstract: The present invention provides a safe and effective vaccine composition which comprises: an effective immunizing amount of an inactivated Ehrlichia canis bacterin; a pharmacologically acceptable carrier; and an immunogenically stimulating amount of an adjuvant system consisting essentially of an antibody response inducing agent and a cell-mediated immunity response inducing agent. The present invention also provides a method for the prevention or amelioration of canine ehrlichiosis in dogs.
    Type: Application
    Filed: April 20, 2006
    Publication date: August 24, 2006
    Applicant: Wyeth
    Inventors: Liangbiao Hu, Thomas Hess, Yu-Wei Chiang, Hsien-Jue Chu
  • Publication number: 20050202046
    Abstract: The present invention provides a safe and effective vaccine composition which comprises: an effective immunizing amount of an inactivated Ehrlichia canis bacterin; a pharmacologically acceptable carrier; and an immunogenically stimulating amount of an adjuvant system consisting essentially of an antibody response inducing agent and a cell-mediated immunity response inducing agent. The present invention also provides a method for the prevention or amelioration of canine ehrlichiosis in dogs.
    Type: Application
    Filed: March 9, 2005
    Publication date: September 15, 2005
    Applicant: Wyeth
    Inventors: Liangbiao (George) Hu, Thomas Hess, Yu-Wei Chiang, Hsien-Jue (Steve) Chu