Patents by Inventor Yu Wei Chou
Yu Wei Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250149379Abstract: A method includes following steps. A semiconductor fin is formed on a substrate. A shallow trench isolation (STI) region is formed around a lower portion of the semiconductor fin. An STI protection layer is over the STI region. After forming the STI protection layer, source/drain recesses are etched in the semiconductor fin. Source/drain epitaxial regions are formed in the source/drain recesses.Type: ApplicationFiled: November 2, 2023Publication date: May 8, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Hung CHEN, Yen-Chun HUANG, Yu-Wei CHOU, Zhen-Cheng WU
-
Publication number: 20250132516Abstract: A connection cable (1) includes an insulation seat (10), a circuit board (20) and a protection cover (30). The insulation seat (10) includes a main body (11) formed with a slot (110) and a conduction opening (111). The conduction opening (111) is connected to the slot (110) and located on the bottom side of the main body (11). The circuit board (20) includes a substrate (21) and a plurality of conductive portions (22) disposed on the substrate (21). The substrate (21) is inserted in the slot (110). The conductive portions (22) are exposed from the conduction opening (111). The protection cover (30) is combined on the main body (11) to shield the conduction opening (111). The protection cover (30) is pushed by the dock connector (2) to expose the conduction opening (111) and to be separated from the main body (11).Type: ApplicationFiled: December 4, 2023Publication date: April 24, 2025Inventors: Shang-Yen HUANG, Wei-Wen CHAN, Yu-Wei CHOU
-
Patent number: 11312882Abstract: A slurry solution for a Chemical Mechanical Polishing (CMP) process includes a wetting agent, a stripper additive that comprises at least one of: N-methyl-2-pyrrolidone (NMP), dimethyl sulfoxide (DMSO), sulfolane, and dimethylformamide (DMF), and an oxidizer additive comprising at least one of: hydrogen peroxide (H2O2), ammonium persulfate ((NH4)2S2O8), peroxymonosulfuric acid (H2SO5), ozone (O3) in de-ionized water, and sulfuric acid (H2SO4).Type: GrantFiled: September 14, 2020Date of Patent: April 26, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Yin Lin, Wen-Kuei Liu, Teng-Chun Tsai, Shen-Nan Lee, Kuo-Cheng Lien, Chang-Sheng Lin, Yu-Wei Chou
-
Patent number: 11011385Abstract: A method of manufacturing an integrated circuit device is provided. A first feature, which has a first susceptibility to damage by chemical mechanical processing (CMP), is formed at a first height as measured from an upper surface of the substrate. A second feature, which has a second susceptibility to damage by the CMP, is formed at a second height as measured from the upper surface of the substrate and is laterally spaced from the first feature by a recess. The second height is greater than the first height, and the second susceptibility is less than the first susceptibility. A sacrificial coating is formed in the recess over an uppermost surface of the first feature. CMP is performed to remove a first portion of the sacrificial coating and expose an upper surface of the second feature while leaving a second portion of the sacrificial coating in place over the first feature.Type: GrantFiled: August 25, 2017Date of Patent: May 18, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Kuei Liu, Teng-Chun Tsai, Kuo-Yin Lin, Shen-Nan Lee, Yu-Wei Chou, Kuo-Cheng Lien, Chang-Sheng Lin, Chih-Chang Hung, Yung-Cheng Lu
-
Publication number: 20200407594Abstract: A slurry solution for a Chemical Mechanical Polishing (CMP) process includes a wetting agent, a stripper additive that comprises at least one of: N-methyl-2-pyrrolidone (NMP), dimethyl sulfoxide (DMSO), sulfolane, and dimethylformamide (DMF), and an oxidizer additive comprising at least one of: hydrogen peroxide (H2O2), ammonium persulfate ((NH4)2S2O8), peroxymonosulfuric acid (H2SO5), ozone (O3) in de-ionized water, and sulfuric acid (H2SO4).Type: ApplicationFiled: September 14, 2020Publication date: December 31, 2020Inventors: Kuo-Yin Lin, Wen-Kuei Liu, Teng-Chun Tsai, Shen-Nan Lee, Kuo-Cheng Lien, Chang-Sheng Lin, Yu-Wei Chou
-
Patent number: 10774241Abstract: A slurry solution for a Chemical Mechanical Polishing (CMP) process includes a wetting agent, a stripper additive that comprises at least one of: N-methyl-2-pyrrolidone (NMP), dimethyl sulfoxide (DMSO), sulfolane, and dimethylformamide (DMF), and an oxidizer additive comprising at least one of: hydrogen peroxide (H2O2), ammonium persulfate ((NH4)2S2O8), peroxymonosulfuric acid (H2SO5), ozone (O3) in de-ionized water, and sulfuric acid (H2SO4).Type: GrantFiled: February 13, 2017Date of Patent: September 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Kuo-Yin Lin, Wen-Kuei Liu, Teng-Chun Tsai, Shen-Nan Lee, Kuo-Cheng Lien, Chang-Sheng Lin, Yu-Wei Chou
-
Patent number: 9852899Abstract: Some embodiments are directed to a wafer polishing tool. The wafer polishing tool includes a first polisher, a second polisher downstream of the first polisher, a third polisher downstream of the second polisher, and a fourth polisher downstream of the third polisher. The first polisher receives a wafer having a front side and a back side with integrated circuit component devices disposed on the front side of the wafer, and polishes a center region on the back side of the wafer. The second polisher receives the wafer via transporting equipment and buffs the center region of the back side of the wafer. The third polisher receives the wafer via the transporting equipment and polishes a back side edge region of the wafer. The fourth polisher receives the wafer via the transporting equipment and buffs the back side edge region of the wafer.Type: GrantFiled: January 17, 2017Date of Patent: December 26, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shen-Nan Lee, Teng-Chun Tsai, Hsin-Hsien Lu, Chang-Sheng Lin, Kuo-Cheng Lien, Kuo-Yin Lin, Wen-Kuei Liu, Yu-Wei Chou
-
Publication number: 20170352548Abstract: A method of manufacturing an integrated circuit device is provided. A first feature, which has a first susceptibility to damage by chemical mechanical processing (CMP), is formed at a first height as measured from an upper surface of the substrate. A second feature, which has a second susceptibility to damage by the CMP, is formed at a second height as measured from the upper surface of the substrate and is laterally spaced from the first feature by a recess. The second height is greater than the first height, and the second susceptibility is less than the first susceptibility. A sacrificial coating is formed in the recess over an uppermost surface of the first feature. CMP is performed to remove a first portion of the sacrificial coating and expose an upper surface of the second feature while leaving a second portion of the sacrificial coating in place over the first feature.Type: ApplicationFiled: August 25, 2017Publication date: December 7, 2017Inventors: Wen-Kuei Liu, Teng-Chun Tsai, Kuo-Yin Lin, Shen-Nan Lee, Yu-Wei Chou, Kuo-Cheng Lien, Chang-Sheng Lin, Chih-Chang Hung, Yung-Cheng Lu
-
Patent number: 9746310Abstract: A method for measuring an implant dosage distribution of a semiconductor sample is provided. The method includes generating a photomodulation effect in a three-dimensional structure of the semiconductor sample and measuring a reflection information of the three-dimensional structure. A geometry information of the three-dimensional structure of the semiconductor sample is obtained. The geometry information of the three-dimensional structure is converted into an estimated reflective data. The reflection information is compared with the estimated reflective data to determine the implant dosage distribution of the three-dimensional structure of the semiconductor sample.Type: GrantFiled: November 6, 2015Date of Patent: August 29, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ying-Chieh Hung, Yi-Hung Lin, Yu-Wei Chou
-
Patent number: 9748109Abstract: An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a polymer coating, CMP to form a planar surface, then plasma etching to effectuate a planar recessing of the polymer coating. The material can be recessed together with the polymer coating, or subsequently with the recessed polymer coating providing a mask. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The polymer can be a photoresist. The polymer can be provided with suitable adhesion and uniformity for the CMP process through a two-step baking process and by exhausting the baking chamber from below the substrate.Type: GrantFiled: February 19, 2016Date of Patent: August 29, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Kuei Liu, Teng-Chun Tsai, Kuo-Yin Lin, Shen-Nan Lee, Yu-Wei Chou, Kuo-Cheng Lien, Chang-Sheng Lin, Chih-Chang Hung, Yung-Cheng Lu
-
Publication number: 20170158914Abstract: A slurry solution for a Chemical Mechanical Polishing (CMP) process includes a wetting agent, a stripper additive that comprises at least one of: N-methyl-2-pyrrolidone (NMP), dimethyl sulfoxide (DMSO), sulfolane, and dimethylformamide (DMF), and an oxidizer additive comprising at least one of: hydrogen peroxide (H2O2), ammonium persulfate ((NH4)2S2O8), peroxymonosulfuric acid (H2SO5), ozone (O3) in de-ionized water, and sulfuric acid (H2SO4).Type: ApplicationFiled: February 13, 2017Publication date: June 8, 2017Inventors: Kuo-Yin Lin, Wen-Kuei Liu, Teng-Chun Tsai, Shen-Nan Lee, Kuo-Cheng Lien, Chang-Sheng Lin, Yu-Wei Chou
-
Publication number: 20170131084Abstract: A method for measuring an implant dosage distribution of a semiconductor sample is provided. The method includes generating a photomodulation effect in a three-dimensional structure of the semiconductor sample and measuring a reflection information of the three-dimensional structure. A geometry information of the three-dimensional structure of the semiconductor sample is obtained. The geometry information of the three-dimensional structure is converted into a estimated reflective data. The reflection information is compared with the estimated reflective data to determine the implant dosage distribution of the three-dimensional structure of the semiconductor sample.Type: ApplicationFiled: November 6, 2015Publication date: May 11, 2017Inventors: Ying-Chieh HUNG, Yi-Hung LIN, Yu-Wei CHOU
-
Publication number: 20170125237Abstract: Some embodiments are directed to a wafer polishing tool. The wafer polishing tool includes a first polisher, a second polisher downstream of the first polisher, a third polisher downstream of the second polisher, and a fourth polisher downstream of the third polisher. The first polisher receives a wafer having a front side and a back side with integrated circuit component devices disposed on the front side of the wafer, and polishes a center region on the back side of the wafer. The second polisher receives the wafer via transporting equipment and buffs the center region of the back side of the wafer. The third polisher receives the wafer via the transporting equipment and polishes a back side edge region of the wafer. The fourth polisher receives the wafer via the transporting equipment and buffs the back side edge region of the wafer.Type: ApplicationFiled: January 17, 2017Publication date: May 4, 2017Inventors: Shen-Nan Lee, Teng-Chun Tsai, Hsin-Hsien Lu, Chang-Sheng Lin, Kuo-Cheng Lien, Kuo-Yin Lin, Wen-Kuei Liu, Yu-Wei Chou
-
Patent number: 9567493Abstract: A method for performing a Chemical Mechanical Polishing (CMP) process includes applying a CMP slurry solution to a surface of a hardened fluid material on a substrate, the solution comprising an additive to change a bonding structure on the surface of the hardened fluid material. The method further includes polishing the surface of the hardened fluid material with a polishing head.Type: GrantFiled: April 25, 2014Date of Patent: February 14, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Yin Lin, Wen-Kuei Liu, Teng-Chun Tsai, Shen-Nan Lee, Kuo-Cheng Lien, Chang-Sheng Lin, Yu-Wei Chou
-
Patent number: 9559021Abstract: A wafer polishing process includes polishing a central area on the back side of a wafer, polishing a peripheral area on the back side of the wafer, buffing the central area, and buffing the peripheral area. The process can significantly reduce scratch-related wafer breakage, can correct focus spots on wafers, and can replace cleaning processes that use chemical etchants. Polishing and buffing can include polishing and buffing the bevel region. Further improvements include polishing with abrasive pads having a soft backing, polishing or buffing with pads having relatively soft abrasive particles, polishing or buffing with abrasive pads made from abrasive particles that have been sorted and selected for regularity of shape, irrigating the surface being polished or buffed with an aqueous solution that includes a friction-reducing agent, and buffing with abrasive pads having 20k or finer grit or non-abrasive pads.Type: GrantFiled: March 4, 2016Date of Patent: January 31, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shen-Nan Lee, Teng-Chun Tsai, Hsin-Hsien Lu, Chang-Sheng Lin, Kuo-Cheng Lien, Kuo-Yin Lin, Wen-Kuei Liu, Yu-Wei Chou
-
Patent number: 9478431Abstract: The present disclosure provides a method of manufacturing an integrated circuit device in some embodiments. In the method, a semiconductor substrate is processed through a series of operations to form a topographically variable surface over the semiconductor substrate. The topographically variable surface varies in height across the semiconductor substrate. A polymeric bottom anti-reflective coating (BARC) is provided over the topographically variable surface. Chemical mechanical polishing is performed to remove a first portion of the BARC, and etching effectuates a top-down recessing of the BARC.Type: GrantFiled: December 14, 2015Date of Patent: October 25, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Kuei Liu, Teng-Chun Tsai, Kuo-Yin Lin, Shen-Nan Lee, Yu-Wei Chou, Kuo-Cheng Lien, Chang-Sheng Lin, Chih-Chang Hung, Yung-Cheng Lu
-
Publication number: 20160190023Abstract: A wafer polishing process includes polishing a central area on the back side of a wafer, polishing a peripheral area on the back side of the wafer, buffing the central area, and buffing the peripheral area. The process can significantly reduce scratch-related wafer breakage, can correct focus spots on wafers, and can replace cleaning processes that use chemical etchants. Polishing and buffing can include polishing and buffing the bevel region. Further improvements include polishing with abrasive pads having a soft backing, polishing or buffing with pads having relatively soft abrasive particles, polishing or buffing with abrasive pads made from abrasive particles that have been sorted and selected for regularity of shape, irrigating the surface being polished or buffed with an aqueous solution that includes a friction-reducing agent, and buffing with abrasive pads having 20k or finer grit or non-abrasive pads.Type: ApplicationFiled: March 4, 2016Publication date: June 30, 2016Inventors: Shen-Nan Lee, Teng-Chun Tsai, Hsin-Hsien Lu, Chang-Sheng Lin, Kuo-Cheng Lien, Kuo-Yin Lin, Wen-Kuei Liu, Yu-Wei Chou
-
Publication number: 20160172209Abstract: An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a polymer coating, CMP to form a planar surface, then plasma etching to effectuate a planar recessing of the polymer coating. The material can be recessed together with the polymer coating, or subsequently with the recessed polymer coating providing a mask. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The polymer can be a photoresist. The polymer can be provided with suitable adhesion and uniformity for the CMP process through a two-step baking process and by exhausting the baking chamber from below the substrate.Type: ApplicationFiled: February 19, 2016Publication date: June 16, 2016Inventors: Wen-Kuei Liu, Teng-Chun Tsai, Kuo-Yin Lin, Shen-Nan Lee, Yu-Wei Chou, Kuo-Cheng Lien, Chang-Sheng Lin, Chih-Chang Hung, Yung-Cheng Lu
-
Publication number: 20160137786Abstract: A copolymer of DCPD-containing benzoxazine (DCPDBz) and cyanate ester resin forms a low-dielectric thermosetting polymeric material for making electronic components. A method of manufacturing the copolymer is also introduced. The method includes allowing DCPD-phenol oligomer, aniline, and paraformaldehyde to react at 110° C. for 6-12 hours before being extracted and baked to obtain DCPDBz; and mixing cyanate ester and the DCPDBz at 150° C.; heating the mixture up to 220° C.Type: ApplicationFiled: November 18, 2014Publication date: May 19, 2016Inventors: WEN-CHIUNG SU, CHING-HSUAN LIN, SHENG-CHEN LIAO, YU-WEI CHOU
-
Patent number: 9321889Abstract: A copolymer of DCPD-containing benzoxazine (DCPDBz) and cyanate ester resin forms a low-dielectric thermosetting polymeric material for making electronic components. A method of manufacturing the copolymer is also introduced. The method includes allowing DCPD-phenol oligomer, aniline, and paraformaldehyde to react at 110° C. for 6-12 hours before being extracted and baked to obtain DCPDBz; and mixing cyanate ester and the DCPDBz at 150° C.; heating the mixture up to 220° C.Type: GrantFiled: November 18, 2014Date of Patent: April 26, 2016Assignee: NATIONAL CHUNG SHAN INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Wen-Chiung Su, Ching-Hsuan Lin, Sheng-Chen Liao, Yu-Wei Chou