Patents by Inventor Yu-Wei Su
Yu-Wei Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12100702Abstract: A method of making a semiconductor device includes manufacturing doped zones in a first semiconductor material over a substrate. The method further includes forming an isolation structure between adjacent doped zones of the first semiconductor material. The method further includes manufacturing lines extending in a first direction over the doped zones of the first semiconductor material, wherein each of the lines has a line width measured along a second direction perpendicular to the first direction. The method further includes trimming the lines into line segments having ends over the isolation structure. The method further includes etching a transistor gate electrode over the substrate, wherein transistor gate electrode has a gate electrode width measured along the second direction, and wherein the line width is substantially similar to the gate electrode width.Type: GrantFiled: October 18, 2023Date of Patent: September 24, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Li-Wei Chu, Wun-Jie Lin, Yu-Ti Su, Ming-Fu Tsai, Jam-Wem Lee
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Production line scheduling method, production line system and non-temporary computer readable medium
Patent number: 12055916Abstract: A production line scheduling method, adapted to a plurality of jobs passing a bottleneck station having at least one manufacturing machine, the jobs respectively correspond to a plurality of job conditions, and the method includes: performing a plurality of times of a schedule simulation algorithm on the jobs to sequentially establish a plurality of schedule simulation trees, and obtaining a job schedule and a simulated finishing period of each job based on the schedule simulation trees; and calculating a plurality of expected feeding times of each job at a plurality of stations including the bottleneck station, each schedule simulation tree includes at least one scheduling route, and each scheduling route is generated from one schedule simulation algorithm, the schedule simulation algorithm includes: performing a node expansion step based on at least one node expansion condition and the job conditions to obtain the scheduling route.Type: GrantFiled: July 9, 2021Date of Patent: August 6, 2024Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-Jung Yeh, Tsan-Cheng Su, Chung-Wei Lin -
Patent number: 12051896Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. When the first transistor is turned on by a detection signal, the first transistor is turned off.Type: GrantFiled: May 24, 2023Date of Patent: July 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Lin Peng, Yu-Ti Su, Chia-Wei Hsu, Ming-Fu Tsai, Shu-Yu Su, Li-Wei Chu, Jam-Wem Lee, Chia-Jung Chang, Hsiang-Hui Cheng
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Patent number: 12051755Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure, with the first terminal including a first portion of a tunneling layer formed on the substrate, and a first gate formed on the first portion of the tunneling layer. The semiconductor structure includes a second terminal coupled to the substrate and adjacent to the first terminal, with the second terminal including a second portion of the tunneling layer formed on the substrate, a second gate formed on the second portion of the tunneling layer, and a dielectric structure formed on a top surface and side surfaces of the second gate. The semiconductor structure includes a third terminal coupled to an insulating structure and adjacent to the second terminal, with the third terminal including, a third gate formed on the insulating structure.Type: GrantFiled: August 31, 2021Date of Patent: July 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chu Lin, Wen-Chih Chiang, Chi-Chung Jen, Ming-Hong Su, Mei-Chen Su, Chia-Wei Lee, Kuan-Wei Su, Chia-Ming Pan
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Publication number: 20240249494Abstract: An environment managing and monitoring system and a method using same are provided. The environment managing and monitoring system is configured to assist monitors to obtain real-time information of the monitoring field and control device in the monitoring field. The environmental managing and monitoring system includes at least one sub-system and a host system. The host system is configured to output a region of interest condition and a monitoring condition to the sub-system, wherein the sub-system is configured to generate monitoring results according to the monitoring conditions, and selects an image range from the captured wide-angle dynamic real-time images according to the region of interest condition.Type: ApplicationFiled: September 4, 2023Publication date: July 25, 2024Inventors: Yung-tai SU, Hsin-lung HSIEH, Yu-hsuan LIAO, Yu-min CHUANG, Pang-tzu LIU, Chun-yueh CHEN, Jia-hao LU, Cheng-ju HSUIEH, Ching-wei LEE, Tsung-hsun TSAI, Po-yuan KUO, Po-yi WU, Chen-wei CHOU
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Patent number: 12038379Abstract: A sanitary device for the urine glucose test includes a urine container formed on an inner wall of a main body, and a measuring module with an inner space mounted at a bottom of the urine container. Within the inner space, a lens attaches to the bottom of the urine container, a rail faces a bottom surface of the lens, and a driving module moves a light unit shooting a detection beam to a measuring surface of the lens along the rail. The measuring surface contacts urine in the urine container, and reflects the detection beam out of the bottom surface into a sensor. The sensor is electrically connected to a processor. The processor determines a urine glucose level and generates a urine glucose level data instantly from an angle of incidence of the detection beam on the measuring surface and from a beam intensity signal from the sensor.Type: GrantFiled: May 18, 2021Date of Patent: July 16, 2024Assignee: Taiwan RedEye Biomedical Inc.Inventors: Shuo-Ting Yan, Tsung-Jui Lin, Yu-Hsun Chen, Kuan-Wei Su
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Patent number: 8506318Abstract: A connector module includes a first connector, a first electrode, a second connector and a second electrode. The first connector has a plug hole. The first electrode is disposed in the plug hole. The second connector has a connecting portion. A projecting area of the connecting portion is larger than that area of the plug hole. The second electrode is disposed at the connecting portion. When the connecting portion is disposed in the first connector, the first electrode contacts the second electrode and an inner wall of the plug hole restrains the connecting portion from detaching from the plug hole. An electronic device with the connector module is also disclosed herein.Type: GrantFiled: January 5, 2012Date of Patent: August 13, 2013Assignee: Asustek Computer Inc.Inventors: Chih-Cheng Liao, Kuo-Wei Tsao, Kuan-Ting Chen, Yu-Wei Su, Min-Hua Hsu
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Publication number: 20120178281Abstract: A connector module includes a first connector, a first electrode, a second connector and a second electrode. The first connector has a plug hole. The first electrode is disposed in the plug hole. The second connector has a connecting portion. A projecting area of the connecting portion is larger than that area of the plug hole. The second electrode is disposed at the connecting portion. When the connecting portion is disposed in the first connector, the first electrode contacts the second electrode and an inner wall of the plug hole restrains the connecting portion from detaching from the plug hole. An electronic device with the connector module is also disclosed herein.Type: ApplicationFiled: January 5, 2012Publication date: July 12, 2012Applicant: ASUSTEK COMPUTER INC.Inventors: Chih-Cheng Liao, Kuo-Wei Tsao, Kuan-Ting Chen, Yu-Wei Su, Min-Hua Hsu
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Patent number: 8213362Abstract: A method for a new node to join an ad-hoc network is provided. The method includes two basic functions. When the new node is allowed to join the network, the indicating device of the node being joined generates an indication. When the new node joins the network, the indicating device of the new node also generates an indication. The method further includes two commands, the join-rejection command and the joined-rejection command, to cancel the join procedure when the indicating device of the new node and the node being joined do not indicate correspondingly. Accordingly, the method efficiently reduces the possibility of joining an unanticipated node.Type: GrantFiled: June 24, 2009Date of Patent: July 3, 2012Assignee: Industrial Technology Research InstituteInventors: Yueh-Feng Lee, Chun-Hao Peng, Yu-Wei Su, Hsin-Sheng Liu
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Publication number: 20100150063Abstract: A method for a new node to join an ad-hoc network is provided. The method includes two basic functions. When the new node is allowed to join the network, the indicating device of the node being joined generates an indication. When the new node joins the network, the indicating device of the new node also generates an indication. The method further includes two commands, the join-rejection command and the joined-rejection command, to cancel the join procedure when the indicating device of the new node and the node being joined do not indicate correspondingly. Accordingly, the method efficiently reduces the possibility of joining an unanticipated node.Type: ApplicationFiled: June 24, 2009Publication date: June 17, 2010Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yueh-Feng Lee, Chun-Hao Peng, Yu-Wei Su, Hsin-Sheng Liu