Patents by Inventor Yu-Wei Tseng

Yu-Wei Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11598806
    Abstract: A test system is disclosed. The test system includes a tester, a first voltage stabilization circuit, and a device under test (DUT). The tester generates a first operational voltage and a control signal. The first voltage stabilization circuit transmits a second operational voltage, associated with the first operational voltage, to a socket board. The DUT operates with the second operational voltage received through the socket board. The first voltage stabilization circuit is further configured to control, according to the control signal, the second operational voltage to have a first voltage level when the DUT is operating.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: March 7, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Yu-Wei Tseng, Chih-Ming Chang, Wan-Chun Fang, Jui-Chung Hsu, Chun-Hsi Li
  • Publication number: 20220359035
    Abstract: A test apparatus configured to test a device under test includes a power supply and a power compensation circuit. The power supply is configured to supply electric power to a power supply terminal of the device under test via a first route or a second route that are connected in parallel. The first route includes a first switch element configured to be controlled according to a first control signal. The power compensation circuit is located on the second route, wherein the power compensation circuit includes a second switch element configured to be controlled according to a second control signal, the power compensation circuit is configured to generate a compensation pulse current when the first switch element is turned off and the second switch element is turned on.
    Type: Application
    Filed: May 10, 2021
    Publication date: November 10, 2022
    Inventors: Chien-Hwa SU, Yu-Wei TSENG, Shang-Ju HSU
  • Publication number: 20220229109
    Abstract: A test system is disclosed. The test system includes a tester, a first voltage stabilization circuit, and a device under test (DUT). The tester generates a first operational voltage and a control signal. The first voltage stabilization circuit transmits a second operational voltage, associated with the first operational voltage, to a socket board. The DUT operates with the second operational voltage received through the socket board. The first voltage stabilization circuit is further configured to control, according to the control signal, the second operational voltage to have a first voltage level when the DUT is operating.
    Type: Application
    Filed: January 21, 2021
    Publication date: July 21, 2022
    Inventors: Yu-Wei TSENG, Chih-Ming CHANG, Wan-Chun FANG, Jui-Chung HSU, Chun-Hsi LI
  • Publication number: 20120049173
    Abstract: An organic field effect transistor (OFET) having a block copolymer (BCP) layer is provided. The OFET includes a gate, an optional dielectric layer, a BCP layer, an organic semiconductor layer, a drain, and a source. The BCP layer is formed between the dielectric layer and the organic semiconductor layer when the dielectric layer exists. Otherwise, the BCP layer is formed between the gate and the organic semiconductor layer when the dielectric layer does not exist. When being positioned between the gate and the organic semiconductor layer without the dielectric layer, the BCP layer also functions as a dielectric layer. Inclusion of the BCP layer enhances the electrical properties, such as the charge carrier mobility, of the OFET.
    Type: Application
    Filed: August 25, 2011
    Publication date: March 1, 2012
    Applicant: NATIONAL CHUNG CHENG UNIVERSITY
    Inventors: Jung-Wei CHENG, Jeng-Rong HO, Chien-Chao TSIANG, Cheng-Yi CHIANG, Yu-Wei TSENG, Ting-Ray CHEN, Chi-Horng CHIEN
  • Patent number: 6956254
    Abstract: A dual bit ROM multilayered structure with improved write and erase functions and a method of manufacturing is disclosed. The structure includes a pair of floating gates at the middle or nitride layer to better define the two locations of electrons representing the dual data bits collected in the middle layer.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: October 18, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Tien Yang, Mu-Yi Lin, Yu-Wei Tseng, Min Ca, Yu-Hua Lee
  • Publication number: 20050116281
    Abstract: A dual bit ROM multilayered structure with improved write and erase functions and a method of manufacturing is disclosed. The structure includes a pair of floating gates at the middle or nitride layer to better define the two locations of electrons representing the dual data bits collected in the middle layer.
    Type: Application
    Filed: December 1, 2003
    Publication date: June 2, 2005
    Inventors: Chin-Tien Yang, Mu-Yi Lin, Yu-Wei Tseng, Min Cao, Yu-Hua Lee