Patents by Inventor Yu-Wei Yeh

Yu-Wei Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240297126
    Abstract: An electronic package is provided in which an electronic component is arranged on a wiring structure and covered with a packaging layer, and a frame body that does not contact the wiring structure is embedded in the packaging layer. Therefore, thermal stress is dispersed through the frame body to avoid warpage of the electronic package, so as to facilitate the arrangement of other electronic components around the electronic component.
    Type: Application
    Filed: May 10, 2024
    Publication date: September 5, 2024
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Chien-Cheng LIN, Ko-Wei CHANG, Yu-Wei YEH, Shun-Yu CHIEN, Chia-Yang CHEN
  • Patent number: 12057409
    Abstract: An electronic package and a manufacturing method of the electronic package are provided, in which an electronic component is arranged on a wiring structure and covered with a packaging layer, and a frame body that does not contact the wiring structure nor cover the electronic component is embedded in the packaging layer.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: August 6, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien Chiu, Wen-Jung Tsai, Chien-Cheng Lin, Ko-Wei Chang, Yu-Wei Yeh, Shun-Yu Chien, Chia-Yang Chen
  • Publication number: 20230082767
    Abstract: An electronic package is provided and uses a plurality of bonding wires as a shielding structure. The bonding wires are stitch bonded onto a carrier carrying electronic components, such that the problem of the shielding structure peeling off or falling off from the carrier can be avoided due to the fact that the bonding wires are not affected by temperature, humidity and other environmental factors.
    Type: Application
    Filed: November 17, 2022
    Publication date: March 16, 2023
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien Chiu, Wen-Jung Tsai, Yu-Wei Yeh, Tsung-Hsien Tsai, Chi-Liang Shih, Sheng-Ming Yang, Ping-Hung Liao
  • Publication number: 20230027120
    Abstract: An electronic package is provided, in which a carrier structure provided with electronic components is disposed onto an antenna structure, where a stepped portion is formed at an edge of the antenna structure, so that a shielding body is arranged along a surface of the stepped portion. Therefore, the shielding body only covers a part of the surface of the antenna structure to prevent the shielding body from interfering with operation of the antenna structure.
    Type: Application
    Filed: August 25, 2021
    Publication date: January 26, 2023
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Shao-Tzu Tang, Wen-Jung Tsai, Chih-Hsien Chiu, Ko-Wei Chang, Yu-Wei Yeh, Yu-Cheng Pai, Chuan-Yi Pan, Chi-Rui Wu
  • Patent number: 11532568
    Abstract: An electronic package is provided and uses a plurality of bonding wires as a shielding structure. The bonding wires are stitch bonded onto a carrier carrying electronic components, such that the problem of the shielding structure peeling off or falling off from the carrier can be avoided due to the fact that the bonding wires are not affected by temperature, humidity and other environmental factors.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: December 20, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien Chiu, Wen-Jung Tsai, Yu-Wei Yeh, Tsung-Hsien Tsai, Chi-Liang Shih, Sheng-Ming Yang, Ping-Hung Liao
  • Publication number: 20210375783
    Abstract: An electronic package is provided and uses a plurality of bonding wires as a shielding structure. The bonding wires are stitch bonded onto a carrier carrying electronic components, such that the problem of the shielding structure peeling off or falling off from the carrier can be avoided due to the fact that the bonding wires are not affected by temperature, humidity and other environmental factors.
    Type: Application
    Filed: July 16, 2020
    Publication date: December 2, 2021
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien Chiu, Wen-Jung Tsai, Yu-Wei Yeh, Tsung-Hsien Tsai, Chi-Liang Shih, Sheng-Ming Yang, Ping-Hung Liao
  • Publication number: 20210351097
    Abstract: An electronic structure and a method for fabricating the same are provided. An electronic component and conductive elements are disposed on a carrier. An encapsulation layer encapsulates the electronic component and the conductive elements. The encapsulation layer has concave portions corresponding in position to the conductive elements. Each of the conductive elements is in no contact with corresponding one of the concave portions.
    Type: Application
    Filed: April 27, 2021
    Publication date: November 11, 2021
    Inventors: Chih-Chiang He, Yu-Wei Yeh, Chia-Yang Chen, Chih-Yi Liao, Chih-Hsien Chiu, Chang-Chao Su
  • Publication number: 20210005524
    Abstract: An electronic structure and a method for fabricating the same are provided. An electronic component and conductive elements are disposed on a carrier. An encapsulation layer encapsulates the electronic component and the conductive elements. The encapsulation layer has concave portions corresponding in position to the conductive elements. Each of the conductive elements is in no contact with corresponding one of the concave portions.
    Type: Application
    Filed: February 18, 2020
    Publication date: January 7, 2021
    Inventors: Chih-Chiang He, Yu-Wei Yeh, Chia-Yang Chen, Chih-Yi Liao, Chih-Hsien Chiu, Chang-Chao Su
  • Patent number: 10818515
    Abstract: The present disclosure provides an electronic package and a method for fabricating the same. A protective layer is formed on a carrier of the electronic component. The electronic component and the protective layer are covered by a covering layer. A through hole is formed in the covering layer and extends through the protective layer, such that a portion of a surface of the carrier is exposed to the through hole. A conductive structure is disposed in the through hole and electrically connected with the carrier. Through the formation of the protective layer, the buffering effect of the protective layer can prevent the laser from directly burning through the covering layer and the protective layer to avoid damages to the carrier.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: October 27, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Wei Yeh, Yen-Hung Lin, Chih-Yi Liao, Chih-Hsien Chiu
  • Publication number: 20200251395
    Abstract: An electronic structure and a method for fabricating the same are provided. An electronic component and conductive elements are disposed on a carrier. An encapsulating layer encapsulates the electronic component and the conductive elements. The encapsulating layer is formed with recessed portions corresponding in position to the conductive elements. A gap is formed between the conductive elements and the recessed portions.
    Type: Application
    Filed: July 2, 2019
    Publication date: August 6, 2020
    Inventors: Chih-Chiang He, Yu-Wei Yeh, Chia-Yang Chen, Chih-Yi Liao, Chih-Hsien Chiu, Chang-Chao Su
  • Publication number: 20200090952
    Abstract: The present disclosure provides an electronic package and a method for fabricating the same. A protective layer is formed on a carrier of the electronic component. The electronic component and the protective layer are covered by a covering layer. A through hole is formed in the covering layer and extends through the protective layer, such that a portion of a surface of the carrier is exposed to the through hole. A conductive structure is disposed in the through hole and electrically connected with the carrier. Through the formation of the protective layer, the buffering effect of the protective layer can prevent the laser from directly burning through the covering layer and the protective layer to avoid damages to the carrier.
    Type: Application
    Filed: November 20, 2018
    Publication date: March 19, 2020
    Inventors: Yu-Wei Yeh, Yen-Hung Lin, Chih-Yi Liao, Chih-Hsien Chiu
  • Patent number: 9378808
    Abstract: A pulse width modulation device for use in an N-ports random access memory having a plurality of word line sets, wherein a specified word line set comprises N port word lines. The pulse width modulation device comprises a status detecting device and a clock signal generator. The status detecting device is coupled to the N port word lines having a first and a second port word line, and outputs a first control signal when both the voltage values of the first and second port word lines are within a first level range. The clock signal generator is coupled to the status detecting device and the specified word line set, and generates and outputs a first clock signal to the specified word line set, wherein a duration of the first clock signal kept within the first level range is variable in response to the first control signal.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: June 28, 2016
    Assignee: M31 Technology Corporation
    Inventors: Nan-Chun Lien, Chen-Wei Lin, Chao-Kuei Chung, Li-Wei Chu, Yuh-Jiun Lin, Yu-Wei Yeh, Wei-Chiang Shih
  • Publication number: 20160111144
    Abstract: A pulse width modulation device for use in an N-ports random access memory having a plurality of word line sets, wherein a specified word line set comprises N port word lines. The pulse width modulation device comprises a status detecting device and a clock signal generator. The status detecting device is coupled to the N port word lines having a first and a second port word line, and outputs a first control signal when both the voltage values of the first and second port word lines are within a first level range. The clock signal generator is coupled to the status detecting device and the specified word line set, and generates and outputs a first clock signal to the specified word line set, wherein a duration of the first clock signal kept within the first level range is variable in response to the first control signal.
    Type: Application
    Filed: January 23, 2015
    Publication date: April 21, 2016
    Inventors: Nan-Chun LIEN, Chen-Wei Lin, Chao-Kuei CHUNG, Li-Wei CHU, Yuh-Jiun LIN, Yu-Wei YEH, Wei-Chiang SHIH
  • Patent number: 9213789
    Abstract: A method of generating optimized memory instances using a memory compiler is disclosed. Data pertinent to describing a memory to be designed are provided, and front-end models and back-end models are made to supply a library. Design criteria are received via a user interface. Design of the memory is optimized among speed, power and area according to the provided library and the received design criteria, thereby generating memory instances.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: December 15, 2015
    Assignee: M31 TECHNOLOGY CORPORATION
    Inventors: Nan-Chun Lien, Hsiao-Ping Lin, Wei-Chiang Shih, Yu-Chun Lin, Yu-Wei Yeh
  • Publication number: 20140173241
    Abstract: A method of generating optimized memory instances using a memory compiler is disclosed. Data pertinent to describing a memory to be designed are provided, and front-end models and back-end models are made to supply a library. Design criteria are received via a user interface. Design of the memory is optimized among speed, power and area according to the provided library and the received design criteria, thereby generating memory instances.
    Type: Application
    Filed: December 13, 2012
    Publication date: June 19, 2014
    Applicant: M31 TECHNOLOGY CORPORATION
    Inventors: Nan-Chun Lien, Hsiao-Ping Lin, Wei-Chiang Shih, Yu-Chun Lin, Yu-Wei Yeh