Abstract: The present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode that provides for low leakage currents within the RRAM cell without using insulating sidewall spacers, and an associated method of formation. In some embodiments, the RRAM cell has a bottom electrode disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A bottom dielectric layer is disposed over the lower metal interconnect layer and/or the lower ILD layer. A dielectric data storage layer having a variable resistance is located above the bottom dielectric layer and the bottom electrode, and a top electrode is disposed over the dielectric data storage layer. Placement of the dielectric data storage layer onto the bottom dielectric layer increases a leakage path distance between the bottom and top electrodes, and thereby provides for low leakage current for the RRAM cell.

Abstract: An integrated circuit device including a resistive random access memory (RRAM) cell formed over a substrate. The RRAM cell includes a top electrode having an upper surface. A blocking layer covers a portion of the upper surface. A via extends above the top electrode within a matrix of dielectric. The upper surface of the top electrode includes an area that interfaces with the blocking layer and an area that interfaces with the via. The area of the upper surface that interfaces with the via surrounds the area of the upper surface that interfaces with the blocking layer. The blocking layer is functional during processing to protect the RRAM cell from etch damage while being structured in such a way as to not interfere with contact between the overlying via and the top electrode.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode that provides for low leakage currents within the RRAM cell without using insulating sidewall spacers, and an associated method of formation. In some embodiments, the RRAM cell has a bottom electrode disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A bottom dielectric layer is disposed over the lower metal interconnect layer and/or the lower ILD layer. A dielectric data storage layer having a variable resistance is located above the bottom dielectric layer and the bottom electrode, and a top electrode is disposed over the dielectric data storage layer. Placement of the dielectric data storage layer onto the bottom dielectric layer increases a leakage path distance between the bottom and top electrodes, and thereby provides for low leakage current for the RRAM cell.

Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a good yield, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer, and forming a variable resistance dielectric data storage layer having a first thickness onto the bottom electrode. A capping layer is formed onto the dielectric data storage layer. The capping layer has a second thickness that is in a range of between approximately 2 to approximately 3 times thicker than the first thickness. A top electrode is formed over the capping layer, and an upper metal interconnect layer is formed over the top electrode.

Abstract: A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. The resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode disposed over the dielectric layer. The first electrode has a sidewall surface. A resistance variable layer has a first portion which is disposed over the sidewall surface of the first electrode and a second portion which extends from the first portion away from the first electrode. A second electrode is over the resistance variable layer.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) cell architecture, with off-axis or laterally offset top electrode via (TEVA) and bottom electrode via (BEVA). Traditional RRAM cells having a TEVA and BEVA that are on-axis can cause high contact resistance variations. The off-axis TEVA and BEVA in the current disclosure pushes the TEVA away from the insulating layer over the RRAM cell, which can improve the contact resistance variations. The present disclosure also relates to a memory device having a rectangular shaped RRAM cell having a larger area that can lower the forming voltage and improve data retention.

Abstract: The present disclosure provides methods of making resistive random access memory (RRAM) cells. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode, a first spacer surrounding the capping layer and a top electrode, a second spacer surround the top portion of the bottom electrode and the first spacer, and the top electrode. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer.

Abstract: A resistive random access memory (RRAM) cell comprises a transistor having a gate and a source/drain region, a bottom electrode having an upper surface coplanar with a top surface of the gate, a resistive material layer on the bottom electrode, a top electrode on the resistive material layer, and a conductive material connecting the bottom electrode to the source/drain region.

Abstract: An easily taken and carried holder for boots is provided with a flexible handle and two holding assemblies secured to both ends of the flexible handle respectively. Each of the holding assemblies comprises an internal space and a magnet in the space. The magnet has two poles so that the magnets of the holding assemblies can attract each other to bring the boots into contact when the holding assembles are inserted into the boots. The flexible handle can be used to take and suspend the boots. The ferromagnetic members can kept the boots upright and prevent the boots from falling to cause wrinkles when the ferromagnetic members are inserted into the boots to be attracted by the magnets. The invention has characteristics of easy taking, secure hold, practicability, and convenient storage.

Abstract: The present disclosure relates to a resistance random access memory (RRAM) device architecture where a Ti metal capping layer is deposited before the deposition of the HK HfO resistance switching layer. Here, the capping layer is below the HK HfO layer, and hence no damage will occur during the top RRAM electrode etching. The outer sidewalls of the capping layer are substantially aligned with the sidewalls of the HfO layer and hence any damage that may occur during future etching steps will happen at the outer side walls of the capping layer that are positioned away from the oxygen vacancy filament (conductive filament) in the HK HfO layer. Thus the architecture in the present disclosure, improves data retention.

Abstract: A method is disclosed that includes the operations outlined below. A first voltage is applied to a gate of an access transistor of each of a row of memory cells during a reset operation, wherein a first source/drain of the access transistor is electrically connected to a first electrode of a resistive random access memory (RRAM) device in the same memory cell. An inhibition voltage is applied to a second electrode of the RRAM device or to a second source/drain of the access transistor of each of a plurality of unselected memory cells when the first voltage is applied to the gate of the access transistor.

Abstract: A method for forming a resistive memory cell within a memory array includes forming a patterned stopping layer on a first metal layer formed on a substrate and forming a bottom electrode into features of the patterned stopping layer. The method further includes forming a resistive memory layer. The resistive memory layer includes a metal oxide layer and a top electrode layer. The method further includes patterning the resistive memory layer so that the top electrode layer acts as a bit line within the memory array and a top electrode of the resistive memory cell.

Abstract: An integrated circuit device including a resistive random access memory (RRAM) cell formed over a substrate. The RRAM cell includes a top electrode having an upper surface. A blocking layer covers a portion of the upper surface. A via extends above the top electrode within a matrix of dielectric. The upper surface of the top electrode includes an area that interfaces with the blocking layer and an area that interfaces with the via. The area of the upper surface that interfaces with the via surrounds the area of the upper surface that interfaces with the blocking layer. The blocking layer is functional during processing to protect the RRAM cell from etch damage while being structured in such a way as to not interfere with contact between the overlying via and the top electrode.

Abstract: The present disclosure provides methods of making resistive random access memory (RRAM) cells. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode, a first spacer surrounding the capping layer and a top electrode, a second spacer surround the top portion of the bottom electrode and the first spacer, and the top electrode. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer.

Abstract: The present disclosure provides a resistive random access memory (RRAM) cell. The RRAM cell includes a transistor, a bottom electrode adjacent to a drain region of the transistor and coplanar with the gate, a resistive material layer on the bottom electrode, a top electrode on the resistive material layer, and a conductive material connecting the bottom electrode to the drain region.

Abstract: A method is disclosed that includes the operations outlined below. A first voltage is applied to a gate of an access transistor of each of a row of memory cells during a reset operation, wherein a first source/drain of the access transistor is electrically connected to a first electrode of a resistive random access memory (RRAM) device in the same memory cell. An inhibition voltage is applied to a second electrode of the RRAM device or to a second source/drain of the access transistor of each of a plurality of unselected memory cells when the first voltage is applied to the gate of the access transistor.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) cell architecture, with off-axis or laterally offset top electrode via (TEVA) and bottom electrode via (BEVA). Traditional RRAM cells having a TEVA and BEVA that are on-axis can cause high contact resistance variations. The off-axis TEVA and BEVA in the current disclosure pushes the TEVA away from the insulating layer over the RRAM cell, which can improve the contact resistance variations. The present disclosure also relates to a memory device having a rectangular shaped RRAM cell having a larger area that can lower the forming voltage and improve data retention.

Abstract: One embodiment in the present disclosure provides a resistor in a resistive random access memory (RRAM). The resistor includes a first electrode; a resistive layer on the first electrode; an electric field enhancement array in the resistive layer; and a second electrode on the resistive layer. The electric field enhancement array includes a plurality of electric field enhancers arranged in a same plane. One embodiment in the present disclosure provides a method of manufacturing a resistor structure in an RRAM. The method comprises (1) forming a first resistive layer on a first electrode; (2) forming a metal layer on the resistive layer; (3) patterning the metal layer to form a metal dot array on the resistive layer; and (4) forming a second electrode on the metal dot array. The metal dot array comprises a plurality of metal dots, and a distance between adjacent metal dots is less than 40 nm.

Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode, a first spacer surrounding the capping layer and a top electrode, a second spacer surround the top portion of the bottom electrode and the first spacer, and the top electrode. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer.

Abstract: A method for forming a resistive memory cell within a memory array includes forming a patterned stopping layer on a first metal layer formed on a substrate and forming a bottom electrode into features of the patterned stopping layer. The method further includes forming a resistive memory layer. The resistive memory layer includes a metal oxide layer and a top electrode layer. The method further includes patterning the resistive memory layer so that the top electrode layer acts as a bit line within the memory array and a top electrode of the resistive memory cell.