Abstract: A shift register includes a plurality of register stages. Each register stage includes an output circuit, a first switching circuit and a second switching circuit. The output circuit is capable of outputting a first driving signal. The first switching circuit is used to pull down the output circuit into a low voltage level when the output circuit is not outputting the first driving signal. The second switching circuit is capable of receiving an input signal. The first switching circuit holds electric charges by the parasitical capacitor resident in the transistor in order to keep the first switching circuit in a turn-on state when the output circuit is not outputting the first driving signal.

Abstract: A shift register for use in an LCD is disclosed. The shift register provides better gate driving signals with the lower coupling effect. The shift register includes two switches. The control node of the first switch is electrically coupled to the control node of the second switch. One end of the first switch receives a clock signal, and the other end of the first switch is electrically coupled to one end of the second switch. The other end of the second switch outputs a gate driving signal. Both of the two switches are controlled by a control signal.

Abstract: A shift register circuit including a first shift register unit, a second shift register unit, a third shift register unit, and a fourth shift register unit connected in serial. The second shift register unit includes an output terminal, and a pull down system pulling the voltage of the output terminal of the second shift register unit according to a pull down signal. The fourth shift register unit includes a third switch and a fourth switch. The fourth switch has a control terminal electrically coupled to the second terminal of the third switch and the pull down unit. The fourth shift register unit generates the pull down signal according to the voltage level of the connecting point between the third switch and the fourth switch.

Abstract: A flat display structure including a substrate, a pixel matrix, a driving circuit and several voltage adapting devices and driving method thereof are provided. Each of voltage adapting devices includes an input terminal, a first control terminal and an output terminal. The input terminal is electrically connected to the i-th gate line Gi corresponding to the i-th pixel row Ri. The first control terminal is adapted to receive a first control signal. The output terminal is adapted to receive a working voltage.

Abstract: A shift register includes a signal generating circuit for generating an output signal at an output end of the shift register according to a first clock signal while the signal generating circuit is turned on; a driving circuit, electrically coupled to the signal generating circuit, for generating a driving signal to control the signal generating circuit according to an input signal received from an input end of the shift register; a feedback circuit, electrically coupled to a next stage shift register, for transmitting a control signal while the feedback circuit is turned on by the next stage shift register; and a control switch, electrically coupled to the signal generating circuit and the feedback circuit, for turning off the signal generating circuit while the control switch is turned on by the control signal from the feedback circuit.

Abstract: A method for driving a panel includes measuring common electrode voltage characteristics of the panel in the X and Y direction of the panel, and modifying driving voltages of the pixel units based on the corresponding measured common electrode voltage characteristics. The pixel units on different locations of the panel can thus be provided with a best symmetric center during the positive and negative driving periods.

Abstract: A system and method for semiconductor work-in-process (WIP) dispatch management. Information regarding multiple wafer lots to be processed in a process node is acquired. Which wafer lot requires processing prior to the other wafer lots is determined by analyzing a load of multiple successive process nodes for each wafer lot. The analyzed quantity of the load of the successive process nodes for each wafer lots is determined contingent upon a predetermined observation time period.

Abstract: A system and method for lot priority adjustment. The system includes a database, a calculation unit and an adjustment unit. The database stores at least a committed date for a lot, a throughput rate and a cycle time for respective route operations in a production line, and Work-In-Process (WIP) information of the production line. The calculation unit calculates an x-ratio for the lot on a target route operation according to a current time, the committed date and a remaining cycle time for the lot, calculates a lot weight for the lot according to current loading of a predetermined number of route operations subsequent to the target route operation, and calculates a weighted x-ratio according to the x-ratio and the lot weight. The adjustment unit adjusts a priority for the lot according to the weighted x-ratio.

Abstract: A gamma correction apparatus comprising a digital to analog converter (DAC), a plurality of compensating circuits, and at least one adjusting circuit is provided. The DAC is used to receive RGB digital signals to further generate analog signals. The analog signals are then transferred to the relative pixel devices through the signal lines on the LCD panel. The compensating circuits inserted between the DAC and the signal lines are used to adjust the analog signals to correct the displaying brightness of the pixel devices. The adjusting circuit connecting to the compensating circuits is used to control the operation of the compensation circuits. In addition, a method for adjusting gamma curves by providing three common voltage levels related to RGB colors individually is also provided to achieve better white balance.