Patents by Inventor Yu Wong

Yu Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200219675
    Abstract: A trigger assembly for use with an electrical device, said electrical device having an electric switch housing with an electrical switch unit disposed therein, the trigger assembly including; a trigger member configured for movement relative to the housing; an actuator member operably-connected to the trigger member and, responsive to movement of the trigger member relative to the housing, said actuator member being movable in a first direction relative to the housing from an OFF position in which the electrical switch is operably-opened by the actuator towards an ON position in which the electrical switch is operably-closed by the actuator, and movable in a second direction relative to the housing from the ON position towards the OFF position; a lock-on mechanism including a first locking member mounted proximate to the trigger member and a second locking member mounted proximate to the housing, wherein when the actuator member is moved in to the ON position, said first and second locking members are selecta
    Type: Application
    Filed: January 3, 2020
    Publication date: July 9, 2020
    Inventor: Kin Yu WONG
  • Patent number: 10685795
    Abstract: A trigger assembly for use with an electrical device, including a trigger member, an actuator member operably-connected to the trigger member, and a lock-on mechanism for selectably restricting movement of the trigger member relative to the housing.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: June 16, 2020
    Assignees: DEFOND ELECTECH CO. LTD., DEFOND COMPONENTS LIMITED
    Inventor: Kin Yu Wong
  • Publication number: 20200185167
    Abstract: A snap-action switch including: a housing in which a plurality of fixed contacts and a plurality of movable contacts are disposed therein, a plunger configured for depressible movement via an aperture in the housing from a first position in which the plunger is relatively extended outwardly of the housing via the aperture, into, a second position in which the plunger is relatively retracted inwardly of the housing via the aperture; and a snap-action assembly operably-connected with the plunger, said snap-action assembly being responsive to depressible movement of the plunger so as to effect snap-action type movement of the plurality of movable contacts between normally opened and normally closed positions with respect to the fixed contacts; a sealing element configured for arrangement around the plunger to occlude ingress of particulates, dust and water from entering the housing via the aperture, said sealing element including a flanged portion; and a securement element configured for arrangement around the s
    Type: Application
    Filed: December 6, 2019
    Publication date: June 11, 2020
    Inventor: Kin Yu Wong
  • Publication number: 20200164090
    Abstract: Polymeric nanoparticles comprising a defined set of biologically active agents that provide for targeted stimulation of non-responsive T cells, e.g. T cells involved in cancer, are provided.
    Type: Application
    Filed: July 27, 2018
    Publication date: May 28, 2020
    Inventors: Qian Yin, Yu Wong, Mark M. Davis
  • Patent number: 10636894
    Abstract: Methods form structures that include (among other components) semiconductor fins extending from a substrate, gate insulators contacting channel regions of the semiconductor fins, and gate conductors positioned adjacent the channel regions and contacting the gate insulators. Additionally, epitaxial source/drain material contacts the semiconductor fins on opposite sides of the channel regions, and source/drain conductive contacts contact the epitaxial source/drain material. Also, first insulating spacers are on the gate conductors. The gate conductors are linear conductors perpendicular to the semiconductor fins, and the first insulating spacers are on both sides of the gate conductors. Further, second insulating spacers are on the first insulating spacers; however, the second insulating spacers are only on the first insulating spacers in locations between where the gate conductors intersect the semiconductor fins.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: April 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yanping Shen, Hui Zang, Hsien-Ching Lo, Qun Gao, Jerome Ciavatti, Yi Qi, Wei Hong, Yongjun Shi, Jae Gon Lee, Chun Yu Wong
  • Publication number: 20200098688
    Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer with a plurality of first conductive lines formed of a first conductive material in a dielectric layer. At least one via opening is formed over the plurality of first conductive lines and an interconnect via formed of a second conductive material is formed in the via opening, wherein the formed interconnect via has a convex top surface.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Inventors: YONGJUN SHI, RUILONG XIE, NAN FU, CHUN YU WONG
  • Publication number: 20200090886
    Abstract: A sealing assembly for prevention of ingress of particulates and water into an electrical switch includes an engagement element with a rigid first abutment portion for circumscribing an aperture extending through the outer surface of the switch housing and a rigid first retention portion. Also included is a sealing element being slidingly engageable with the engagement element that includes a first complementary abutment portion. The sealing element is formed from an elastically resilient polymeric material so that sealing engagement with the engagement element occludes passage and ingress of external particulates, dust and water.
    Type: Application
    Filed: November 20, 2019
    Publication date: March 19, 2020
    Applicants: Defond Electech Co., Ltd., Defond Components Limited
    Inventor: Kin Yu WONG
  • Publication number: 20200060450
    Abstract: The utility model relates to an article for daily use, namely a foldable compact memory foam travel neck pillow, which includes a pillow body and a support body, with the pillow body being equipped with a cavity to accommodate the support body; the support body consists of an elastic support (C/U-shaped) and two underpinning supports, with the two underpinning supports being respectively fixed at both ends of the elastic support in a rotational way. The utility model performs well in underpinning force, and can be used, worn and packaged in a convenient way.
    Type: Application
    Filed: November 7, 2018
    Publication date: February 27, 2020
    Inventor: May Yu WONG
  • Publication number: 20200020631
    Abstract: One illustrative integrated circuit product disclosed herein includes a vertically oriented semiconductor (VOS) structure positioned above a semiconductor substrate, a conductive silicide vertically oriented e-fuse positioned along at least a portion of a vertical height of the VOS structure wherein the conductive silicide vertically oriented e-fuse comprises a metal silicide material that extends through at least a portion of an entire lateral width of the VOS structure, and a conductive metal silicide region in the semiconductor substrate that is conductively coupled to the conductive silicide vertically oriented e-fuse.
    Type: Application
    Filed: September 23, 2019
    Publication date: January 16, 2020
    Inventors: Chun Yu Wong, Kwan-Yong Lim, Seong Yeol Mun, Jagar Singh, Hui Zang
  • Patent number: 10510662
    Abstract: One illustrative method disclosed herein comprises forming a vertically oriented semiconductor (VOS) structure in a semiconductor substrate and performing a metal silicide formation process to convert at least a portion of the VOS structure into a metal silicide material, thereby forming a conductive silicide vertically oriented e-fuse.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Chun Yu Wong, Kwan-Yong Lim, Seong Yeol Mun, Jagar Singh, Hui Zang
  • Publication number: 20190371796
    Abstract: First and second fin-type field effect transistors (finFETs) are formed laterally adjacent one another extending from a top surface of an isolation layer. The first finFET has a first fin structure and the second finFET has a second fin structure. An insulator layer is on the first fin structure and the second fin structure. A gate conductor intersects the first fin structure and the second fin structure, and at least the insulator layer separates the gate conductor from the first fin structure and the second fin structure. Source and drain structures are on the first fin structure and the second fin structure laterally adjacent the gate conductor. The first fin structure has sidewalls that include a step and the second fin structure has sidewalls that do not include the step. The step is approximately parallel to the surface of the isolation layer.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 5, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Garo Jacques Derderian, Laertis Economikos, Chun Yu Wong, Jiehui Shu, Shesh Mani Pandey
  • Patent number: 10497523
    Abstract: A sealing assembly for prevention of ingress of particulates and water into an electrical switch includes an engagement element with a rigid first abutment portion for circumscribing an aperture extending through the outer surface of the switch housing and a rigid first retention portion. Also included is a sealing element being slidingly engageable with the engagement element that includes a first complementary abutment portion. The sealing element is formed from an elastically resilient polymeric material so that sealing engagement with the engagement element occludes passage and ingress of external particulates, dust and water.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: December 3, 2019
    Assignees: Defond Electech Co., Ltd., Defond Components Limited
    Inventor: Kin Yu Wong
  • Patent number: 10475791
    Abstract: First and second fin-type field effect transistors (finFETs) are formed laterally adjacent one another extending from a top surface of an isolation layer. The first finFET has a first fin structure and the second finFET has a second fin structure. An insulator layer is on the first fin structure and the second fin structure. A gate conductor intersects the first fin structure and the second fin structure, and at least the insulator layer separates the gate conductor from the first fin structure and the second fin structure. Source and drain structures are on the first fin structure and the second fin structure laterally adjacent the gate conductor. The first fin structure has sidewalls that include a step and the second fin structure has sidewalls that do not include the step. The step is approximately parallel to the surface of the isolation layer.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: November 12, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Garo Jacques Derderian, Laertis Economikos, Chun Yu Wong, Jiehui Shu, Shesh Mani Pandey
  • Patent number: 10468481
    Abstract: A methodology for forming a single diffusion break structure in a FinFET device involves localized, in situ oxidation of a portion of a semiconductor fin. Fin oxidation within a fin cut region may be preceded by the formation of epitaxial source/drain regions over the fin, as well as by a gate cut module, where portions of a sacrificial gate that straddle the fin are replaced by an isolation layer. Localized oxidation of the fin enables the stress state in adjacent, un-oxidized portions of the fin to be retained, which may beneficially impact carrier mobility and hence conductivity within channel portions of the fin.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Hui Zang, Chun Yu Wong, Kwan-Yong Lim
  • Patent number: 10461029
    Abstract: Methods of forming a hybrid electrically programmable fuse (e-fuse) structure and the hybrid e-fuse structure are disclosed. In various embodiments, the e-fuse structure includes: a substrate; an insulator layer over the substrate; a pair of contact regions overlying the insulator layer; and a silicide channel overlying the insulator layer and connecting the pair of contact regions, the silicide channel having a first portion including silicide silicon and a second portion coupled with the first portion and on a common level with the first portion, the second portion including silicide silicon germanium (SiGe) or silicide silicon phosphorous (SiP).
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: October 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chun Yu Wong, Jagar Singh
  • Patent number: 10439026
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fin structures with single diffusion break facet improvement using an epitaxial insulator and methods of manufacture. The structure includes: a plurality of fin structures; an insulator material filling a cut between adjacent fin structures of the plurality of fin structures; a metal material (e.g., rare earth oxide or SrTiO3) at least partially lining the cut; and an epitaxial source region or epitaxial drain region in at least one of the plurality of fin structures and adjacent to the metal material.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: October 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chun Yu Wong, Hui Zang, Xusheng Wu
  • Patent number: 10418285
    Abstract: Methods of forming a CT pillar with reduced width and increased distance from neighboring fins and the resulting devices are provided. Embodiments include providing a first pair of fins and a second pair of fins in an oxide layer, wherein the first and second pair of fins include Si; and forming a CT pillar including SiN between the first and second pair of fins and over a portion of the oxide layer, wherein width of the CT pillar and distance between the CT pillar and the first and second pair of fins are inversely proportional.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: September 17, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Chun Yu Wong, Laertis Economikos
  • Patent number: 10418195
    Abstract: A contact lever for use in an electrical switch assembly so as to allow selectable movement within the switch assembly of a contact lever contact member from electrical connection with a first stationary contact member into electrical connection with a second stationary contact member, the contact lever including: first and second lever arms that are connected at respective first ends to the contact lever contact member; said first and second lever arms having respective second ends, and, said first and second lever arms being configured to extend away from the contact member and to terminate at their respective second ends; a gap disposed between the first and second lever arms which separates the first and second lever arms as they extend away from the contact member, and wherein the gap is configured to allow movement of a spring element of the switch assembly therethrough; and a bridge member configured for connection with the first and second lever arms so as to traverse the gap separating the first and
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: September 17, 2019
    Assignee: Defond Electech Co., Ltd
    Inventor: Kin Yu Wong
  • Publication number: 20190280105
    Abstract: Methods form structures that include (among other components) semiconductor fins extending from a substrate, gate insulators contacting channel regions of the semiconductor fins, and gate conductors positioned adjacent the channel regions and contacting the gate insulators. Additionally, epitaxial source/drain material contacts the semiconductor fins on opposite sides of the channel regions, and source/drain conductive contacts contact the epitaxial source/drain material. Also, first insulating spacers are on the gate conductors. The gate conductors are linear conductors perpendicular to the semiconductor fins, and the first insulating spacers are on both sides of the gate conductors. Further, second insulating spacers are on the first insulating spacers; however, the second insulating spacers are only on the first insulating spacers in locations between where the gate conductors intersect the semiconductor fins.
    Type: Application
    Filed: March 9, 2018
    Publication date: September 12, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Yanping Shen, Hui Zang, Hsien-Ching Lo, Qun Gao, Jerome Ciavatti, Yi Qi, Wei Hong, Yongjun Shi, Jae Gon Lee, Chun Yu Wong
  • Publication number: 20190229183
    Abstract: A methodology for forming a single diffusion break structure in a FinFET device involves localized, in situ oxidation of a portion of a semiconductor fin. Fin oxidation within a fin cut region may be preceded by the formation of epitaxial source/drain regions over the fin, as well as by a gate cut module, where portions of a sacrificial gate that straddle the fin are replaced by an isolation layer. Localized oxidation of the fin enables the stress state in adjacent, un-oxidized portions of the fin to be retained, which may beneficially impact carrier mobility and hence conductivity within channel portions of the fin.
    Type: Application
    Filed: January 19, 2018
    Publication date: July 25, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Haiting WANG, Hui ZANG, Chun Yu WONG, Kwan-Yong LIM