Abstract: The present application provides a power battery voltage regulation circuit, including a power battery, a heating module, a charging and discharging interface, and a voltage regulation switch assembly; the heating module includes an energy storage element and a switch module; the power battery and the switch module are connected in parallel; an external charging and discharging device is connected in parallel with the power battery through the charging and discharging interface; the voltage regulation switch assembly includes multiple switches, and the multiple switches are arranged between the charging and discharging interface and the power battery; and the voltage regulation switch assembly and the switch module are configured to adjust the charging and discharging voltages between the external charging and discharging device and the power battery in response to a voltage regulation control signal.

Abstract: Disability-related information of a user of a computing device can be acquired, the computing device can present a scene with user interface elements to the user. An accessibility requirement of the user can be identified based on the acquired disability-related information of the user. A processing routine can be determined from a plurality of processing routines stored in a routine library based on the accessibility requirement of the user. One or more of the user interface elements of the scene can be modified using the determined processing routine. The scene with the modified one or more of the user interface elements can be presented to the user through the computing device.

Abstract: The present disclosure provides an array substrate and a display device. The array substrate includes: a plurality of gate lines extending in a first direction, and a plurality of data lines extending in a second direction and crossing the gate lines to define a plurality of sub-pixels; a plurality of touch signal lines extending in the second direction and arranged in light shielding regions of the sub-pixels; a plurality of touch electrodes insulated from each other; and a plurality of metal pattern units corresponding to the sub-pixels respectively and arranged in the light shielding region of each sub-pixel. The metal pattern unit includes a first metal strip arranged on at least one side of the data line and extending in the second direction.

Abstract: The disclosure discloses a method, an apparatus, a device, and a storage medium for interaction. The method of interaction includes: in response to detecting that a first user enters a virtual room, displaying a shooting task list in the virtual room; the shooting task list containing a plurality of shooting tasks, and each shooting task carries task information; obtaining, for the shooting task, an image taken by the first user based on the task information carried by the shooting task; performing a feature extraction on the image to obtain feature information; and comparing the feature information with the task information, and determining that the shooting task is completed if the feature information matches the task information.

Abstract: Embodiments of the present disclosure relate to a method, an apparatus, an electronic device, and a medium for data transfer. The method includes generating, based on metadata of to-be-transferred data and a blockchain including a data transfer record, an ownership certificate of an initiator of a transfer for the to-be-transferred data. The method further includes generating a new transfer record for validation by a blockchain system, where the new transfer record includes the ownership certificate and validation information associated with a receiver of the transfer. The method further includes transferring the to-be-transferred data to the receiver in response to that the new transfer record passes validation of the blockchain system. In this way, the data transfer record may be reliably stored in the blockchain, thereby providing reliable integrity protection and data traceability for a storage system.

Abstract: An alternating electric field-driven gallium nitride (GaN)-based nano-light-emitting diode (nanoLED) structure with an electric field enhancement effect is provided. The GaN-based nanoLED structure forms a nanopillar structure that runs through an indium tin oxide (ITO) layer, a p-type GaN layer, a multiple quantum well (MQW) active layer and an n-type GaN layer and reaches a GaN buffer layer; and the nanopillar structure has a cross-sectional area that is smallest at the MQW active layer and gradually increases towards two ends of a nanopillar, forming a pillar structure with a thin middle and two thick ends. The shape of the GaN-based nanopillar improves the electric field strength within the QW layer in the alternating electric field environment and increases the current density in the QW region of the nanopillar structure under current driving, forming strong electric field gain and current gain, thereby improving the luminous efficiency of the device.

Abstract: Methods and apparatuses for improving the performance and energy efficiency of Radio Access Networks (RANs) are described. Various power control schemes may dynamically adjust RAN power consumption based on fluctuations in network traffic, throughput, latency, queue sizes, and/or packet error rates with the goal of increasing energy efficiency while maintaining quality of service metrics. The power control schemes may be implemented using a PRB controller for dynamically allocating physical resource blocks (PRBs) to user devices and a CPU controller for assigning CPU power profiles based on PRB allocations for the user devices. The PRB controller and CPU controller may periodically acquire real-time telemetry data and wireless network performance information and then adjust the number of PRBs for user devices and adjust the CPU power profiles for executing RAN functions based on the telemetry data and wireless network performance information.

Abstract: Methods and apparatuses for improving the performance and energy efficiency of Radio Access Networks (RANs) are described. Various power control schemes may dynamically adjust RAN power consumption based on fluctuations in network traffic, throughput, latency, queue sizes, and/or packet error rates with the goal of increasing energy efficiency while maintaining quality of service metrics. The power control schemes may be implemented using a PRB controller for dynamically allocating physical resource blocks (PRBs) to user devices and a CPU controller for assigning CPU power profiles based on PRB allocations for the user devices. The PRB controller and CPU controller may periodically acquire real-time telemetry data and wireless network performance information and then adjust the number of PRBs for user devices and adjust the CPU power profiles for executing RAN functions based on the telemetry data and wireless network performance information.

Abstract: A charging state analysis method of an electric vehicle based on electrical characteristic sequence analysis is provided. The method includes following steps: step S1, obtaining voltage sampling data and current sampling data of the electric vehicle during charging; step S2, setting a time interval, so as to divide the voltage sample data and the current sampling data obtained in step S1 into multiple data sets; step S3, calculating an electrical characteristic vector of each time interval; step S4. adding the calculation results of Step S3 to a temperature sensing value T, and generate an electrical characteristic sequence of whole charging cycle; step S5, inputting the electrical characteristic sequence of the electric vehicle into a trained TRNN in sequence to obtain corresponding results; if the result is 1, it is normal; if the result is 0, it is abnormal.

Abstract: A semiconductor structure includes a base structure, a first portion, a second portion and a first stack. The first portion and the second portion are disposed on the base structure and are respectively made of a first semiconductor material and a second semiconductor material which has a conductivity type opposite to that of the first semiconductor material. The first stack is disposed on the base structure and between the first portion and the second portion. The first stack includes a plurality of first semiconductor regions and a plurality of first dielectric regions disposed to alternate with the first semiconductor regions, such that each of the first semiconductor regions and the first dielectric regions extends between the first portion and the second portion. The first semiconductor regions has a dopant concentration which is lower than that of each of the first portion and the second portion.

Abstract: A semiconductor structure includes a base structure, at least one diode device and a semiconductor device. The base structure has a first base region and a second base region. The at least one diode device includes a first feature formed in the first base region, and a second feature formed over the first feature and having a conductivity type opposite to that of the first feature. The semiconductor device is formed on the second base region.

Abstract: A display substrate comprises a base substrate (10), a first conductive layer (21), a first planarization layer (31), a second conductive layer (22), a second planarization layer (32) and at least one transparent conductive layer which are located on the base substrate (10). The second conductive layer (22) is electrically connected with the first conductive layer (21) through at least one first via penetrating the first planarization layer (31). The transparent conductive layer includes at least one first transparent conductive line (231) and at least one auxiliary trace (232). An orthographic projection of the first transparent conductive line (231) on the base substrate (10) is overlapped with an orthographic projection of the at least one first via on the base substrate (10).

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.

Abstract: An array substrate, a display panel and a display device. In the array substrate, the plurality of pixel units are located on a side of a base substrate; the common electrode line includes a horizontal common electrode line and a vertical common electrode line, the horizontal common electrode line is electrically connected with the vertical common electrode line, the plurality of pixel units are arranged in an array to form a plurality of pixel rows and a plurality of pixel columns, each of the pixel rows extends along the first direction, and each of the pixel columns extends along the second direction, the horizontal common electrode line extends along the first direction, the vertical common electrode line extends along the second direction, the horizontal common electrode line is overlapped with a plurality of effective display regions of a same pixel row.

Abstract: A thermal module may include a cold plate including a cold plate base having a cold plate base protruding portion, and a cold plate cover on the cold plate base, and a heat pipe between the cold plate base and the cold plate cover, and including an upper heat pipe portion and a lower heat pipe portion in the cold plate base protruding portion.

Abstract: A housing for an electronic device can include an exterior titanium portion, an interior metal joined to the exterior titanium portion, the interior metal being a different metal than the exterior titanium portion, and an intermetallic compound having a thickness of less than 1 ?m disposed between the interior metal and the exterior titanium portion.

Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.

Abstract: A housing for an electronic device can include an exterior titanium portion, an interior metal joined to the exterior titanium portion, the interior metal being a different metal than the exterior titanium portion, and an intermetallic compound having a thickness of less than 1 ?m disposed between the interior metal and the exterior titanium portion.

Abstract: The present application relates to a system, apparatus, and method of detecting anomalies in configurations of computer systems. A computer may execute a configuration analyzer to infer a configuration template that is applicable to multiple configuration files. The configuration analyzer configuration uses unsupervised learning on the configuration template to score parameters within each configuration file. The configuration analyzer indicates an anomaly for a parameter of a configuration file exceeding a threshold score. Inferring a configuration template may include generating a lowest cost template that is applicable to two of the multiple configuration files based on a cost function; and combining the lowest cost template with a subsequent configuration file of the multiple configuration files to generate an updated lowest cost template until the updated lowest cost template is applicable to all of the multiple configuration files.

Abstract: A housing for an electronic device can include an exterior titanium portion, an interior metal joined to the exterior titanium portion, the interior metal being a different metal than the exterior titanium portion, and an intermetallic compound having a thickness of less than 1 ?m disposed between the interior metal and the exterior titanium portion.