Abstract: An electronic package is provided in which an electronic component is arranged on a wiring structure and covered with a packaging layer, and a frame body that does not contact the wiring structure is embedded in the packaging layer. Therefore, thermal stress is dispersed through the frame body to avoid warpage of the electronic package, so as to facilitate the arrangement of other electronic components around the electronic component.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: An optoelectronic semiconductor device includes a substrate, a first type semiconductor structure, a second type semiconductor structure, an active structure and a contact structure. The first type semiconductor structure is located on the substrate and has a first protrusion part with a first thickness and a platform part with a second thickness. The second type semiconductor structure is located on the first type semiconductor structure. The active structure is between the first type semiconductor structure and the second type semiconductor structure. The contact structure is disposed between the first type semiconductor structure and the substrate. The second thickness of the platform part is in a range of 0.01 ?m to 1 ?m.

Abstract: An image calibration method is applied to an image calibration device includes an image receiver and an operation processor. The image calibration method of providing a motion deblur function includes driving a first camera to capture a first image having a first exposure time, driving a second camera disposed adjacent to the first camera to capture a second image having a second exposure time different from and at least partly overlapped with the first exposure time, and fusing a first feature of the first image and a second feature of the second image to generate a fusion image.

Abstract: A frame rate control method is provided. A primary scenario and a non-primary scenario are identified according to two or more windows displayed on a screen. Each of the primary scenario and the non-primary scenario is performed by an individual application. A frame rate of the non-primary scenario is decreased when a performance index indicates that a first condition is present. The application corresponding to the non-primary scenario is disabled when the performance index indicates that a second condition is present after decreasing the frame rate of the non-primary scenario, so as to remove the window corresponding to the non-primary scenario from the screen.

Abstract: A PET hydrolase having high enzymatic activity is disclosed. The PET hydrolase has a modified amino acid sequence of SEQ ID NO: 2. The modified enzyme has improved PET-hydrolytic activity, thereby obtaining the high-yield and high-activity PET hydrolase, and enhancing the industrial application value of the PET hydrolase.

Abstract: An electronic package and a manufacturing method of the electronic package are provided, in which an electronic component is arranged on a wiring structure and covered with a packaging layer, and a frame body that does not contact the wiring structure nor cover the electronic component is embedded in the packaging layer.

Abstract: A time-interleaved analog-to-digital converter (TIADC) operates in a first mode or a second mode and includes M analog-to-digital converters (ADCs), a reference ADC, a digital correction circuit, and a control circuit. The M ADCs sample an input signal according to M enable signals to generate M digital output codes. The reference ADC samples the input signal according to a reference enable signal to generate a reference digital output code. The digital correction circuit corrects the M digital output codes to generate M corrected digital output codes. The control circuit generates the M enable signals and the reference enable signal according to a clock. The control circuit outputs the M corrected digital output codes in turn but does not output the reference digital output code in the first mode and randomly outputs the M corrected digital output codes and the reference digital output code in the second mode.

Abstract: A method for measuring a thickness of a thin film layer disposed on a piece of glass is implemented using a computer device that stores a thin film image of the thin film layer, a surface dataset associated with a surface of the thin film layer, and a plurality of reference parameter sets each being associated with a specific thickness of the thin film layer, the method including: generating a spectral image dataset that includes spectral data associated with different pixels of the thin film image using a spectral transformation matrix; performing regression analysis on the surface dataset and the spectral image dataset, so as to obtain a thickness parameter set including a plurality of thickness parameters; and determining a thickness of the thin film layer using the thickness parameter set and the plurality of reference parameter sets.

Abstract: A data storage device includes a controller, a data storage unit, a microprocessor, and a network communication unit. The controller includes a firmware. The data storage unit includes a first system storage sector and a second system storage sector. The first system storage sector stores an original operating system, and the second system storage sector stores a backup operating system. When the data storage device receives an operating system differential file from a cloud management platform, the firmware updates the backup operating system in the second system storage sector to obtain a new version of backup operating system. Accordingly, the backup operating system of the data storage device can be quickly updated by downloading a small file size of the operating system differential file so as to enhance the convenience for the updating of the backup operating system.

Abstract: A method of fabricating a semiconductor device includes forming a memory gate and a hard mask layer on the memory gate, forming a select gate on a sidewall of the memory gate and the hard mask layer, performing a selective oxidation process to form an oxide layer on the hard mask layer and the select gate, wherein a portion of the oxide layer on the select gate is thicker than a portion of the oxide layer on the hard mask layer, and removing the oxide layer on the hard mask layer and the hard mask layer to expose a top surface of the memory gate.

Abstract: A method of fabricating a semiconductor device includes forming a memory gate and a hard mask layer on the memory gate, forming a select gate on a sidewall of the memory gate and the hard mask layer, performing a selective oxidation process to form an oxide layer on the hard mask layer and the select gate, wherein a portion of the oxide layer on the select gate is thicker than a portion of the oxide layer on the hard mask layer, and removing the oxide layer on the hard mask layer and the hard mask layer to expose a top surface of the memory gate.

Abstract: A method of manufacturing a semiconductor device includes providing a silicon substrate with multiple layers formed on a front side and a backside, wherein at least a dielectric layer is formed on the backside of the silicon substrate; defining isolation regions and active regions at the front side of the silicon substrate, wherein the active regions are separated by the isolation regions; treating the multiple layers formed at the front side and the backside of the silicon substrate, so as to remain the dielectric layer as an outermost layer exposed at the backside of the silicon substrate; and depositing a polysilicon layer on the isolation regions and the active regions at the front side of the silicon substrate.

Abstract: The present invention provides a flash cell structure and a method of fabricating the same. The flash cell structure includes a semiconductor substrate, a stacked gate structure disposed on the semiconductor substrate, a first doped region disposed in the semiconductor substrate at a side of the stacked gate structure, a first dielectric layer, a second dielectric layer, and an erase gate. The stacked gate structure includes a floating gate insulated from the semiconductor substrate and a control gate disposed on the floating gate and insulated from the floating gate. The first dielectric layer is disposed on a sidewall of the floating gate. The second dielectric layer is disposed on the first doped region. A thickness of the first dielectric layer is less than a thickness of the second dielectric layer.

Abstract: A semiconductor fabricating apparatus includes a reaction chamber, a first gas pipeline, and a second gas pipeline. The first gas pipeline includes a first cleaning gas pipeline for providing a first cleansing gas to the reaction chamber in a cleansing process, and a second cleansing gas pipeline for providing a second cleansing gas to the reaction chamber in the cleansing process. The first cleansing gas pipeline and the second cleansing gas pipeline are connected in parallel. The second gas pipeline provides a reactive gas to the reaction chamber in a fabricating process. The first gas pipeline and the second gas pipeline are connected in parallel.

Abstract: The present invention discloses a clock generator circuit for generating an output clock signal. The clock generator circuit includes: a random frequency code generator for generating a frequency code randomly, wherein the random frequency code generator is clocked by a first clock signal; an accumulator electrically connected to the random frequency code generator, for generating a selection code by accumulating the frequency code, wherein the accumulator is clocked by the first clock signal; a first multiplexer electrically connected to the accumulator, for selecting one of a plurality of reference clock signals as the first clock signal according to the selection code; and a toggle circuit electrically connected to the first multiplexer, being clocked by the first clock signal for generating the output clock signal.

Abstract: The present invention discloses a clock generator circuit for generating an output clock signal. The clock generator circuit includes: a random frequency code generator for generating a frequency code randomly, wherein the random frequency code generator is clocked by a first clock signal; an accumulator electrically connected to the random frequency code generator, for generating a selection code by accumulating the frequency code, wherein the accumulator is clocked by the first clock signal; a first multiplexer electrically connected to the accumulator, for selecting one of a plurality of reference clock signals as the first clock signal according to the selection code; and a toggle circuit electrically connected to the first multiplexer, being clocked by the first clock signal for generating the output clock signal.