Abstract: A controller includes a body and a surrounding part. The body has a control area for sending a control signal according to a movement of a thumb of a user. The surrounding part is connected to the body and used to surround and be fixed to a proximal phalange of an index finger of the user. The body is away from a joint between the proximal phalange and a metacarpal bone of the user.

Abstract: Systems and methods for efficient convolution based on matrix multiply and add (MMA) are described. An example processor having a plurality of processing lanes is configured to perform convolution of a matrix of activation elements and a filter matrix in accordance with a configurable series of instructions including a plurality of MMA instructions and shift instructions while reusing activation elements already loaded to the datapath or associated memory over a plurality of MMA operations. Associated methods are also described.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of nanostructures formed over a substrate, and an inner spacer layer between two adjacent nanostructures. The semiconductor structure includes a source/drain (S/D) structure formed adjacent to the inner spacer layer, and a barrier layer adjacent to the inner spacer layer. The barrier layer extends from the first position to the second position, and the first position is between the inner spacer layer and the nanostructure, and the second position is between the nanostructures and the S/D structure.

Abstract: Embodiments of the present disclosure provide a method for selectively forming a seed layer over semiconductor fins. Some embodiments provide forming the selective seed layer using a mono-silane at an increased temperature. Some embodiments provide depositing a hetero-crystalline silicon cap layer over the bottom-up gap layer to improve gap filling and tune profiles of fin structures.

Abstract: The present disclosure provides a fusion protein and the nucleic acid encoding sequence thereof, and uses of the same. The fusion protein of the present disclosure achieves the effect of treating cancer, immunoregulation and activating immune cells through various efficacy experiments.

Abstract: A fast-transient buffer is shown. The fast-transient buffer has a flipped voltage follower coupled between the input terminal and the output terminal of the fast-transient buffer, and a first MOS transistor coupled to the flipped voltage follower as well as the output terminal of the fast-transient buffer. The first MOS transistor regulates the output voltage of the output terminal of the fast-transient buffer, in the opposite direction in comparison with an output voltage regulation direction due to the flipped voltage follower.

Abstract: A data storage device includes a controller, a data storage unit, a microprocessor, and a network communication unit. The controller includes a firmware. The data storage unit includes a first system storage sector and a second system storage sector. The first system storage sector stores an original operating system, and the second system storage sector stores a backup operating system. When the data storage device receives an operating system differential file from a cloud management platform, the firmware updates the backup operating system in the second system storage sector to obtain a new version of backup operating system. Accordingly, the backup operating system of the data storage device can be quickly updated by downloading a small file size of the operating system differential file so as to enhance the convenience for the updating of the backup operating system.

Abstract: A layout routing method includes determining a routing pattern according to a swapping rule, a via pattern, area constraints and pin locations; optimizing swapping in differential pairs according to the routing pattern; extracting features of each routing net to obtain extracted features; using an unsupervised algorithm to generate different routing groups according to the extracted features; and determining a routing order of the routing groups according to complex features of the routing groups.

Abstract: A method for measuring a thickness of a thin film layer disposed on a piece of glass is implemented using a computer device that stores a thin film image of the thin film layer, a surface dataset associated with a surface of the thin film layer, and a plurality of reference parameter sets each being associated with a specific thickness of the thin film layer, the method including: generating a spectral image dataset that includes spectral data associated with different pixels of the thin film image using a spectral transformation matrix; performing regression analysis on the surface dataset and the spectral image dataset, so as to obtain a thickness parameter set including a plurality of thickness parameters; and determining a thickness of the thin film layer using the thickness parameter set and the plurality of reference parameter sets.

Abstract: A data storage device includes a controller, a data storage unit, a microprocessor, and a network communication unit. The controller includes a firmware. The data storage unit includes a first system storage sector and a second system storage sector. The first system storage sector stores an original operating system, and the second system storage sector stores a backup operating system. When the data storage device receives an operating system differential file from a cloud management platform, the firmware updates the backup operating system in the second system storage sector to obtain a new version of backup operating system. Accordingly, the backup operating system of the data storage device can be quickly updated by downloading a small file size of the operating system differential file so as to enhance the convenience for the updating of the backup operating system.

Abstract: A method of fabricating a semiconductor device includes forming a memory gate and a hard mask layer on the memory gate, forming a select gate on a sidewall of the memory gate and the hard mask layer, performing a selective oxidation process to form an oxide layer on the hard mask layer and the select gate, wherein a portion of the oxide layer on the select gate is thicker than a portion of the oxide layer on the hard mask layer, and removing the oxide layer on the hard mask layer and the hard mask layer to expose a top surface of the memory gate.

Abstract: A method of fabricating a semiconductor device includes forming a memory gate and a hard mask layer on the memory gate, forming a select gate on a sidewall of the memory gate and the hard mask layer, performing a selective oxidation process to form an oxide layer on the hard mask layer and the select gate, wherein a portion of the oxide layer on the select gate is thicker than a portion of the oxide layer on the hard mask layer, and removing the oxide layer on the hard mask layer and the hard mask layer to expose a top surface of the memory gate.

Abstract: A method of manufacturing a semiconductor device includes providing a silicon substrate with multiple layers formed on a front side and a backside, wherein at least a dielectric layer is formed on the backside of the silicon substrate; defining isolation regions and active regions at the front side of the silicon substrate, wherein the active regions are separated by the isolation regions; treating the multiple layers formed at the front side and the backside of the silicon substrate, so as to remain the dielectric layer as an outermost layer exposed at the backside of the silicon substrate; and depositing a polysilicon layer on the isolation regions and the active regions at the front side of the silicon substrate.

Abstract: The present invention provides a flash cell structure and a method of fabricating the same. The flash cell structure includes a semiconductor substrate, a stacked gate structure disposed on the semiconductor substrate, a first doped region disposed in the semiconductor substrate at a side of the stacked gate structure, a first dielectric layer, a second dielectric layer, and an erase gate. The stacked gate structure includes a floating gate insulated from the semiconductor substrate and a control gate disposed on the floating gate and insulated from the floating gate. The first dielectric layer is disposed on a sidewall of the floating gate. The second dielectric layer is disposed on the first doped region. A thickness of the first dielectric layer is less than a thickness of the second dielectric layer.

Abstract: A semiconductor fabricating apparatus includes a reaction chamber, a first gas pipeline, and a second gas pipeline. The first gas pipeline includes a first cleaning gas pipeline for providing a first cleansing gas to the reaction chamber in a cleansing process, and a second cleansing gas pipeline for providing a second cleansing gas to the reaction chamber in the cleansing process. The first cleansing gas pipeline and the second cleansing gas pipeline are connected in parallel. The second gas pipeline provides a reactive gas to the reaction chamber in a fabricating process. The first gas pipeline and the second gas pipeline are connected in parallel.

Abstract: The present invention discloses a clock generator circuit for generating an output clock signal. The clock generator circuit includes: a random frequency code generator for generating a frequency code randomly, wherein the random frequency code generator is clocked by a first clock signal; an accumulator electrically connected to the random frequency code generator, for generating a selection code by accumulating the frequency code, wherein the accumulator is clocked by the first clock signal; a first multiplexer electrically connected to the accumulator, for selecting one of a plurality of reference clock signals as the first clock signal according to the selection code; and a toggle circuit electrically connected to the first multiplexer, being clocked by the first clock signal for generating the output clock signal.

Abstract: The present invention discloses a clock generator circuit for generating an output clock signal. The clock generator circuit includes: a random frequency code generator for generating a frequency code randomly, wherein the random frequency code generator is clocked by a first clock signal; an accumulator electrically connected to the random frequency code generator, for generating a selection code by accumulating the frequency code, wherein the accumulator is clocked by the first clock signal; a first multiplexer electrically connected to the accumulator, for selecting one of a plurality of reference clock signals as the first clock signal according to the selection code; and a toggle circuit electrically connected to the first multiplexer, being clocked by the first clock signal for generating the output clock signal.