Abstract: An example electronic device includes a controller to determine a user touch detection by a power adaptor coupled to the electronic device to operate the electronic device in an AC power mode. The power adaptor may comprise a proximity sensor to detect a user touch for detachment of the power adaptor from the electronic device, and a control circuit to operate a configuration pin in a low output mode to signal user touch detection. The controller may initiate central processing unit (CPU) throttling to reduce power consumption by the electronic device. The controller may further stop CPU throttling in response to detecting that the power adaptor has been detached from the electronic device. Further, the controller may switch the electronic device to a DC power mode to operate using DC power supplied by a battery of the electronic device in response to power adaptor detachment.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method includes forming a first dielectric bonding layer over a first dielectric structure, which is disposed on a first substrate and surrounds a first plurality of interconnects. The first dielectric bonding layer is patterned to form a first recess exposing one of the first plurality of interconnects. A first conductive bonding segment is formed within the first recess. A second dielectric bonding layer is formed over a TSV extending through a second substrate. The second dielectric bonding layer is patterned to form a second recess exposing the TSV. A second conductive bonding segment is formed within the second recess. The first substrate is bonded to the second substrate along an interface comprising dielectric and conductive regions. The conductive region includes a conductive interface between the first and second conductive bonding segments.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects within a first dielectric structure on a first substrate, and a second plurality of interconnects within a second dielectric structure on a second substrate. A bonding structure is arranged between the first dielectric structure and the second substrate. An inter-tier interconnect structure extends between the first plurality of interconnects and the second plurality of interconnects and through the second substrate. The inter-tier interconnect structure includes a first region having substantially vertical sidewalls extending through the second substrate and a second region surrounded by the bonding structure. The second region contacts a bottom of the first region and has tapered sidewalls.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a first through substrate via (TSV) within a substrate. The first TSV comprises a first doped region extending from a top surface of the substrate to a bottom surface of the substrate. A conductive via overlies the top surface of the substrate and is electrically coupled to the first TSV.

Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects within a first dielectric structure on a first substrate, and a second plurality of interconnects within a second dielectric structure on a second substrate. A bonding structure is arranged between the first dielectric structure and the second substrate. An inter-tier interconnect structure extends between the first plurality of interconnects and the second plurality of interconnects and through the second substrate. The inter-tier interconnect structure includes a first region having substantially vertical sidewalls extending through the second substrate and a second region surrounded by the bonding structure. The second region contacts a bottom of the first region and has tapered sidewalls.

Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components.

Abstract: The present disclosure, in some embodiments, relates to a multi-dimensional integrated chip structure. The structure includes a first interconnect layer within a first dielectric structure on a first substrate, and a second interconnect layer within a second dielectric structure on a second substrate. A bonding structure is between the first dielectric structure and the second substrate. An inter-tier interconnect structure extends through the second substrate and between a top of the first interconnect layer and a bottom of the second interconnect layer. The inter-tier interconnect structure includes a first region having substantially vertical sidewalls extending through the second substrate and a second region below the first region and having tapered sidewalls surrounded by the bonding structure.

Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a first through substrate via (TSV) within a substrate. The first TSV comprises a first doped region extending from a top surface of the substrate to a bottom surface of the substrate. A conductive via overlies the top surface of the substrate and is electrically coupled to the first TSV.

Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first through substrate via (TSV) within a first semiconductor substrate. The first semiconductor substrate has a front-side surface and a back-side surface respectively on opposite sides of the first semiconductor substrate. The first semiconductor substrate includes a first doped channel region extending from the front-side surface to the back-side surface. The first through substrate via (TSV) is defined at least by the first doped channel region. A first interconnect structure on the front-side surface of the first semiconductor substrate. The first interconnect structure includes a plurality of first conductive wires and a plurality of first conductive vias, and the first conductive wires and the first conductive vias define a conductive path to the first TSV.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first through substrate via (TSV) within a first semiconductor substrate. The first semiconductor substrate has a front-side surface and a back-side surface respectively on opposite sides of the first semiconductor substrate. The first semiconductor substrate includes a first doped channel region extending from the front-side surface to the back-side surface. The first through substrate via (TSV) is defined at least by the first doped channel region. A first interconnect structure on the front-side surface of the first semiconductor substrate. The first interconnect structure includes a plurality of first conductive wires and a plurality of first conductive vias, and the first conductive wires and the first conductive vias define a conductive path to the first TSV.

Abstract: The present disclosure, in some embodiments, relates to a multi-dimensional integrated chip structure. The structure includes a first interconnect layer within a first dielectric structure on a first substrate, and a second interconnect layer within a second dielectric structure on a second substrate. A bonding structure is between the first dielectric structure and the second substrate. An inter-tier interconnect structure extends through the second substrate and between a top of the first interconnect layer and a bottom of the second interconnect layer. The inter-tier interconnect structure includes a first region having substantially vertical sidewalls extending through the second substrate and a second region below the first region and having tapered sidewalls surrounded by the bonding structure.

Abstract: The present disclosure relates to a method of forming a multi-dimensional integrated chip having tiers connected in a front-to-back configuration, and an associated apparatus. In some embodiments, the method is performed by forming one or more semiconductor devices within a first substrate, forming one or more image sensing elements within a second substrate, and bonding a first dielectric structure over the first substrate to a back-side of the second substrate by way of a bonding structure. An inter-tier interconnect structure, comprising a plurality of different segments, respectively having sidewalls with different sidewall angles, is formed to extend through the bonding structure and the second substrate. The inter-tier interconnect structure is configured to electrically couple a first metal interconnect layer over the first substrate to a second metal interconnect layer over the second substrate.

Abstract: The present disclosure relates to a method of forming a multi-dimensional integrated chip having tiers connected in a front-to-back configuration, and an associated apparatus. In some embodiments, the method is performed by forming one or more semiconductor devices within a first substrate, forming one or more image sensing elements within a second substrate, and bonding a first dielectric structure over the first substrate to a back-side of the second substrate by way of a bonding structure. An inter-tier interconnect structure, comprising a plurality of different segments, respectively having sidewalls with different sidewall angles, is formed to extend through the bonding structure and the second substrate. The inter-tier interconnect structure is configured to electrically couple a first metal interconnect layer over the first substrate to a second metal interconnect layer over the second substrate.