Abstract: An apparatus includes a phase-locked loop and a jitter detection circuit. A method of detecting a jitter in the apparatus includes the phase-locked loop generating a lead control signal and a lag control signal according to a reference clock and a feedback clock, the jitter detection circuit generating a jitter signal according to the lead control signal and the lag control signal, the jitter detection circuit generating a jitter window signal according to the jitter signal, the jitter detection circuit identifying jitters in the clock signal according to the jitter signal and the jitter window signal, and the jitter detection circuit outputting a jitter indication signal according to the number of jitters identified.

Abstract: An integrated circuit includes a signal generating unit, a signal monitoring unit and a processing unit. The signal generating unit is configured to generate a control signal. The signal monitoring unit is configured to receive the control signal and accordingly output a monitor signal. The processing unit is configured to receive the monitor signal. The control signal is adjusted until the monitor signal is located within a preset range. A signal monitoring method used with the integrated circuit and a signal monitoring method used with a plurality of transistors are also provided.

Abstract: An integrated circuit includes a signal generating unit, a signal monitoring unit and a processing unit. The signal generating unit is configured to generate a control signal. The signal monitoring unit is configured to receive the control signal and accordingly output a monitor signal. The processing unit is configured to receive the monitor signal. The control signal is adjusted until the monitor signal is located within a preset range. A signal monitoring method used with the integrated circuit and a signal monitoring method used with a plurality of transistors are also provided.

Abstract: A phase-locked loop (PLL) and a method for controlling the PLL are provided. The PLL includes a phase detector, a charge pump, a voltage-controlled oscillator (VCO), a feedback frequency divider, and a detector circuit. The phase detector generates a direction signal according to a comparison between phases of a first clock signal and a second clock signal. The charge pump converts the direction signal into a control voltage. The VCO generates a third clock signal. The control voltage controls a frequency of the third clock signal. The feedback frequency divider divides the frequency of the third clock signal to generate the second clock signal. The detector circuit sends a pulse signal to restart the VCO when the control voltage conforms to a preset condition.

Abstract: A circuit and a method for restarting up a VCO of a PLL are introduced herein. The VCO restart up circuit receives a power down signal, an external signal, a clock output from the VCO and generates a trigger signal to the VCO to trigger the VCO clock to leave a stable mode. In other words, if the VCO clock is in the stable mode, the VCO restart up circuit generates one or more than one pulse on a trigger signal to restart up the VCO. Oppositely, if the VCO is not in the stable mode, there is no pulse on the trigger signal generated by the VCO restart up circuit and the VCO needs not to be restarted up.

Abstract: A circuit and a method for restarting up a VCO of a PLL are introduced herein. The VCO restart up circuit receives a power down signal, an external signal, a clock output from the VCO and generates a trigger signal to the VCO to trigger the VCO clock to leave a stable mode. In other words, if the VCO clock is in the stable mode, the VCO restart up circuit generates one or more than one pulse on a trigger signal to restart up the VCO. Oppositely, if the VCO is not in the stable mode, there is no pulse on the trigger signal generated by the VCO restart up circuit and the VCO needs not to be restarted up.

Abstract: An asynchronous successive approximation register analog-to-digital converter includes a clock generator, a logic control unit, a sample and hold circuit, a digital-to-analog converter and a comparator. The clock generator is used to generate a clock signal. The logic control unit is for generating a sample and hold clock according to the clock signal. The sample and hold circuit is for sampling an analog signal according to the sample and hold clock to obtain and hold a sampling signal. The digital-to-analog converter is for generating a reference value according to a digital value transmitted from the logic control unit. The comparator is for generating a comparison value according to the sampling signal and the reference value.

Abstract: A DAC has at least one bit current-steering circuit. In the DAC, the current-steering circuit has a current source circuit, a switch, a feedback circuit, and an amplifier circuit. The current source circuit is disposed for outputting a bias current to the switch and coupled to the amplifier circuit. The switch has a first input/output terminal coupled to output an analog signal, a control terminal coupled to the feedback circuit, and a second input/output terminal for receiving the bias current, so that the first switch determines whether the first and the second input/output terminals are conducted according to a status of the control terminal.

Abstract: A digital-to-analog converter includes a clock driver, a first decoder, a second decoder, a current source matrix, a pseudo random mode generator and at least one multiplexer. The first decoder and the second decoder are coupled to the clock driver. The current source matrix is coupled to the first decoder, and the pseudo random mode generator is used to randomly output a set of selecting signals. Each multiplexer of the at least one multiplexer includes a plurality of input ends coupled to a plurality of output ends of the second decoder, an output end coupled to the current source matrix, and a select end coupled to the pseudo random mode generator for controlling the output end to output a bit signal inputted from the input ends of the multiplexer according to one selecting signal of the set of selecting signals.

Abstract: A frequency-converting circuit and a down converter with the frequency-converting circuit are disclosed. The above-mentioned frequency-converting circuit is used for converting an RF signal into a first baseband signal according to a poly-phase LO signal. The frequency-converting circuit includes a coupler, a first transduction unit and a first switching unit. The coupler is for receiving and splitting the RF signal and delivering a first RF signal via the first output terminal thereof. The first transduction unit is for amplifying the first RF signal. The first switching unit is for performing switching operations on the output signal of the first transduction unit and producing the first baseband signal.

Abstract: A frequency-converting circuit and a down converter with the frequency-converting circuit are disclosed. The above-mentioned frequency-converting circuit is used for converting an RF signal into a first baseband signal according to a poly-phase LO signal. The frequency-converting circuit includes a coupler, a first transduction unit and a first switching unit. The coupler is for receiving and splitting the RF signal and delivering a first RF signal via the first output terminal thereof. The first transduction unit is for amplifying the first RF signal. The first switching unit is for performing switching operations on the output signal of the first transduction unit and producing the first baseband signal.

Abstract: A transmit-receive switch for ultrawideband and a method for isolating transmitting and receiving signal thereof are provided. The transmit-receive switch includes a first switch, a second switch, and an inductor. The first switch has a first end coupled to a signal transmitting end, a second end coupled to a signal transmit-receive end, and a control end receiving a first control signal to decide whether or not to turn on the first switch according to the first controlling signal. The second switch has a first end coupled to a signal receiving end, a second end coupled to the signal transmit-receive end, and a control end receiving a second control signal to decide whether or not to turn on the second switch according to the second controlling signal. The inductor has an end coupled to the signal transmit-receive end, and another end coupled to a first potential.

Abstract: A capacitor structure has a plurality of stacked conductive patterns, and each conductive pattern has a closed conductive ring, a plurality of major conductive bars arranged in parallel and electrically to the closed conductive ring, and a plurality of minor conductive bars arranged alternately with the major conductive bars and not electrically connected to the closed conductive ring. The major conductive bars and the minor conductive bars of an odd layer conductive pattern are respectively corresponding to the minor conductive bars and the major conductive bars of an even layer conductive pattern.

Abstract: A capacitor structure has a plurality of stacked conductive patterns, and each conductive pattern has a closed conductive ring, a plurality of major conductive bars arranged in parallel and electrically to the closed conductive ring, and a plurality of minor conductive bars arranged alternately with the major conductive bars and not electrically connected to the closed conductive ring. The major conductive bars and the minor conductive bars of an odd layer conductive pattern are respectively corresponding to the minor conductive bars and the major conductive bars of an even layer conductive pattern.