Patents by Inventor Yu-Yen Chang
Yu-Yen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12185497Abstract: A fluid immersion cooling system has a fluid tank containing a hydrocarbon dielectric fluid as a coolant fluid. One or more components of an electronic system is immersed in the coolant fluid. A gas cylinder contains a non-flammable, compressed filling gas. The temperature of the coolant fluid is monitored during operation of the electronic system. The filling gas is released from the gas cylinder and into the fluid tank when the temperature of the coolant fluid rises to a trigger temperature that is set based on the flash point of the coolant fluid. The filling gas covers a surface of the coolant fluid to block oxygen from interacting with vapors of the coolant fluid to prevent combustion.Type: GrantFiled: August 19, 2022Date of Patent: December 31, 2024Assignee: Super Micro Computer, Inc.Inventors: Yueh-Ming Liu, Hsiao-Chung Chen, Chia-Wei Chen, Yu-Hsiang Huang, Chia-Che Chang, Hua-Kai Tong, Tan-Hsin Chang, Yu-Chuan Chang, Ming-Yu Chen, Yu-Yen Hsiung, Kun-Chieh Liao
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Publication number: 20240424164Abstract: The present disclosure relates to medical implant components comprising a biocompatible protective coating layer (BPCL) and a process of making the BPCL and medical implant components.Type: ApplicationFiled: May 2, 2024Publication date: December 26, 2024Applicant: INNOJET TECHNOLOGY CO., LTD.Inventors: Jen-Hsien CHANG, Wei-Cheng TANG, Yu-Yen TSAI
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Patent number: 12166015Abstract: A semiconductor package includes a lower semiconductor device, a plurality of conductive pillars, an upper semiconductor device, an encapsulating material, and a redistribution structure. The plurality of conductive pillars are disposed on the lower semiconductor device along a direction parallel to a side of the lower semiconductor device. The upper semiconductor device is disposed on the lower semiconductor device and reveals a portion of the lower semiconductor device where the plurality of conductive pillars are disposed, wherein the plurality of conductive pillars disposed by the same side of the upper semiconductor device and the upper semiconductor device comprises a cantilever part cantilevered over the at least one lower semiconductor device. The encapsulating material encapsulates the lower semiconductor device, the plurality of conductive pillars, and the upper semiconductor device. The redistribution structure is disposed over the upper semiconductor device and the encapsulating material.Type: GrantFiled: March 16, 2023Date of Patent: December 10, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Kang Hsieh, Hung-Yi Kuo, Hao-Yi Tsai, Kuo-Lung Pan, Ting Hao Kuo, Yu-Chia Lai, Mao-Yen Chang, Po-Yuan Teng, Shu-Rong Chun
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Publication number: 20240395550Abstract: A method for fabricating a semiconductor device is provided. The method includes coating a photoresist film over a target layer over a semiconductor substrate; performing a lithography process to pattern the photoresist film into a photoresist layer; performing a directional ion bombardment process to the photoresist layer along a direction tilted with respect to a normal direction of the semiconductor substrate, such that a carbon atomic concentration in the photoresist layer is increased; and etching the target layer using the photoresist layer as an etch mask.Type: ApplicationFiled: July 30, 2024Publication date: November 28, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Tien SHEN, Chih-Kai YANG, Hsiang-Ming CHANG, Chun-Yen CHANG, Ya-Hui CHANG, Wei-Ting CHIEN, Chia-Cheng CHEN, Liang-Yin CHEN
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Publication number: 20240387149Abstract: The current disclosure includes a plasma etching system that includes a movable plasma source and a moveable wafer stage. A relative position between the movable plasma source and the movable wafer stage can be varied to set up an angle along which plasma particles of the plasma hits a wafer positioned on the wafer stage.Type: ApplicationFiled: July 29, 2024Publication date: November 21, 2024Inventors: Chun-Yen CHANG, Yu-Tien SHEN, Chih-Kai YANG, Ya-Hui CHANG, Shih-Ming CHANG
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Publication number: 20240363398Abstract: A semiconductor die is provided. The semiconductor die includes a substrate having a front surface, a rear surface opposite to the front surface, and a sidewall connected between the front surface and the rear surface. The sidewall includes a first primary segment immediately connected to the front surface, a second primary segment immediately connected to the rear surface, and a middle segment between the first primary segment and the second primary segment. The slope of the second primary segment is less than the slope of the first primary segment, and the slope of the middle segment is less than the slope of the second primary segment. Each of the first primary segment, the second primary segment, and the middle segment is a flat surface having a slope greater than 0 degrees relative to a line parallel to the front surface of the substrate.Type: ApplicationFiled: July 5, 2024Publication date: October 31, 2024Inventors: Yu-Sheng TANG, Fu-Chen CHANG, Cheng-Lin HUANG, Wen-Ming CHEN, Chun-Yen LO, Kuo-Chio LIU
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Publication number: 20240345211Abstract: An electronic device and a control method thereof are provided. The electronic device includes a DSP (Digital Signal Processor). The DSP receives a digital signal. The digital signal includes a plurality of frames. The DSP divides the plurality of frames into a vital group and a non-vital group according to a criterion. The DSP compares a total number of frames of the vital group with a threshold value. In response to the total number of frames of the vital group being greater than the threshold value, the DSP may calculate signal strength of the vital group.Type: ApplicationFiled: June 8, 2023Publication date: October 17, 2024Inventors: Chuan Yen KAO, Yu Wen HUANG, Wei Rong TSENG, Yao Tsung CHANG, Yin Yu CHEN
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Publication number: 20240320706Abstract: A terminal includes one or more processors, and memory storing one or more computer programs configured to be executed by the one or more processors. The one or more computer programs include instructions for: displaying an analysis screen of a livestream associated with a selling item on a display; and displaying, on the analysis screen, a first object indicating a sales activity on a livestreamer side and a second object indicating reactions on viewers side together along a same time axis.Type: ApplicationFiled: October 16, 2023Publication date: September 26, 2024Inventors: Hao-Jung LO, Chia-Yi YANG, Yu-Hsin CHIANG, Cheng-Chieh CHANG, Sheng-Yen WANG, Liang-Fang TSAI
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Patent number: 12096657Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated semiconducting oxide transistors. The semiconducting oxide transistors may exhibit different device characteristics. Some of the semiconducting oxide transistors may be formed using a first oxide layer formed from a first semiconducting oxide material using first processing steps, whereas other semiconducting oxide transistors are formed using a second oxide layer formed from a second semiconducting oxide material using second processing steps different than the first processing steps. The display may include three or more different semiconducting oxide layers formed during different processing steps.Type: GrantFiled: October 18, 2021Date of Patent: September 17, 2024Assignee: Apple Inc.Inventors: Jung Yen Huang, Shinya Ono, Chin-Wei Lin, Akira Matsudaira, Cheng Min Hu, Chih Pang Chang, Ching-Sang Chuang, Gihoon Choo, Jiun-Jye Chang, Po-Chun Yeh, Shih Chang Chang, Yu-Wen Liu, Zino Lee
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Patent number: 12094691Abstract: The current disclosure includes a plasma etching system that includes a movable plasma source and a moveable wafer stage. A relative position between the movable plasma source and the movable wafer stage can be varied to set up an angle along which plasma particles of the plasma hits a wafer positioned on the wafer stage.Type: GrantFiled: July 7, 2021Date of Patent: September 17, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Yen Chang, Yu-Tien Shen, Chih-Kai Yang, Ya-Hui Chang, Shih-Ming Chang
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Patent number: 12087618Abstract: A method for sawing a semiconductor wafer is provided. The method includes sawing the semiconductor wafer with a first dicing blade to form a first opening. The semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape. The first opening is formed in the upper portion of the substrate. The method also includes sawing the semiconductor wafer with a second dicing blade from the first opening to form a second opening under the first opening and in the middle portion of the substrate. The method further includes sawing the semiconductor wafer with a third dicing blade from the second opening to form a third opening under the second opening and penetrating the lower portion of the substrate, so that the semiconductor wafer is divided into two dies. The first dicing blade, the second dicing blade, and the third dicing blade have different widths.Type: GrantFiled: April 15, 2021Date of Patent: September 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Sheng Tang, Fu-Chen Chang, Cheng-Lin Huang, Wen-Ming Chen, Chun-Yen Lo, Kuo-Chio Liu
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Publication number: 20240290703Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.Type: ApplicationFiled: May 8, 2024Publication date: August 29, 2024Inventors: Kuo-Lung Pan, Yu-Chia Lai, Teng-Yuan Lo, Mao-Yen Chang, Po-Yuan Teng, Chen-Hua YU, Chung-Shi Liu, Hao-Yi Tsai, Tin-Hao Kuo
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Publication number: 20240251568Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.Type: ApplicationFiled: April 4, 2024Publication date: July 25, 2024Inventors: Tai-Yen Peng, Tsung-Hsien Chang, Yu-Shu Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Chung-Te Lin
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Publication number: 20130099089Abstract: A mould assembly with a heating device comprises: an upper mould with an upper joint surface, a lower mould, two conductive plates and two conductive wires. The lower mould includes a conductive layer, a lower joint surface which is formed on the conductive layer and faces the upper joint surface, an insulating surface which is formed on the conductive layer and faces in an opposite direction from the lower joint surface, an insulating formed on the insulating surface. The two conductive plates are disposed on the conductive layer of the lower mould. The two conductive wires are connected to the conductive plates and each have a resistivity lower than a resistivity of the conductive layer. The mould assembly with a heating device is low cost and capable of making the temperature distribution on the surface of the mould assembly more uniform.Type: ApplicationFiled: September 10, 2012Publication date: April 25, 2013Applicants: Kunshan Yurong Electronics Co., Ltd.Inventors: YU-YEN CHANG, Chung-Nan Liu
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Patent number: 7810645Abstract: A platform for securely mounting a wafer cassette holder thereon is provided which includes a wafer cassette holder that has a flat bottom surface and four sidewall panels, a platform that has a flat top surface larger than and for mating to the flat bottom surface of the wafer cassette holder, And a securing device mounted in the flat top surface of the platform juxtaposed to each side of the four sidewalls of the wafer cassette holder for preventing the holder from accidentally slipping off the platform, the securing device may include either a plurality of engagement pins that slidingly engages the wafer cassette holder for securely holding the holder on the platform, or a plurality of side panels mounted along the peripheral edge of the platform for preventing the holder from slipping off the platform.Type: GrantFiled: July 3, 2002Date of Patent: October 12, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Hung Huang, Ching-Chiang Chang, Yu-Yen Chang, Pei-Yi Kuo, Kuo-Chen Lin, Chung-Yi Lee
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Publication number: 20060127203Abstract: A cassette stocker and method of forming the same. The cassette stocker comprises a housing, at least one operation device, and a transferring device. The housing comprises a plurality of openings. The operation device is disposed corresponding to the openings and storing a cassette. The transferring device is disposed in the housing, retrieving and transferring the cassette stored in the operation device via the openings.Type: ApplicationFiled: May 4, 2005Publication date: June 15, 2006Inventors: Yu-Yen Chang, Hung-Wei Chen, Chien-Tien Lin
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Publication number: 20050036857Abstract: An automatic material handing system (AMHS). The AMHS comprises a rail, an overhead shuttle (OHS) and a stocker. The OHS moves on the rail. An in/out port (I/O port) is disposed in the stocker. The rail passes through the stocker and enters the I/O port. When the OHS is in the I/O port, a transport device places goods directly into the OHS.Type: ApplicationFiled: March 3, 2004Publication date: February 17, 2005Inventors: Hung-Wei Chen, Yu-Yen Chang
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Publication number: 20040265099Abstract: A conveyer system. The conveyer system includes a stocker and a conveyor. The stocker has a first position and a second position. The conveyor, with an Input/Output port, enters the stocker, wherein the Input/Output port is disposed between the first position and the second position.Type: ApplicationFiled: February 26, 2004Publication date: December 30, 2004Inventors: Yu-Yen Chang, Hung-Wei Chen
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Patent number: 6739820Abstract: Within both a stocker apparatus and a method for operating the stocker apparatus there is employed: (1) a minimum of six input/output ports; (2) an array of storage locations for storing an array of work in process (WIP) product units; and (3) a random access transportation means for transporting a work in process (WIP) product unit at least bidirectionally between the minimum of six input/output ports and a storage location within the array of storage locations. Within the stocker apparatus and the method, the minimum of six input/output ports provides for more efficient operation of the stocker apparatus.Type: GrantFiled: January 16, 2001Date of Patent: May 25, 2004Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Yu-Yen Chang, Kuo-Chen Lin
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Publication number: 20040004167Abstract: A platform for securely mounting a wafer cassette holder thereon is provided which includes a wafer cassette holder that has a flat bottom surface and four sidewall panels, a platform that has a flat top surface larger than and for mating to the flat bottom surface of the wafer cassette holder, and a securing means mounted in the flat top surface of the platform juxtaposed to each side of the four sidewalls of the wafer cassette holder for preventing the holder from accidentally slipping off the platform. The securing means may include either a plurality of engagement pins that slidingly engages the wafer cassette holder for securely holding the holder on the platform, or a plurality of side panels mounted along the peripheral edge of the platform for preventing the holder from slipping off the platform.Type: ApplicationFiled: July 3, 2002Publication date: January 8, 2004Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Hung Huang, Ching-Chiang Chang, Yu-Yen Chang, Pei-Yi Kuo, Kuo-Chen Lin, Chung-Yi Lee