Patents by Inventor Yu-Yen Chang
Yu-Yen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250095724Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.Type: ApplicationFiled: December 2, 2024Publication date: March 20, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang, Li-Ping Huang, Yu-Fang Chen, Chun-Yen Tseng, Tzu- Feng Chang, Chun-Chieh Chang
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Publication number: 20250096203Abstract: A manufacturing method of a semiconductor package includes the following steps. A first lower semiconductor device and a second lower semiconductor device are provided. A plurality of first conductive pillars are formed on the first lower semiconductor device along a first direction parallel to a side of the first lower semiconductor device. A plurality of second conductive pillars are formed on the second lower semiconductor device along a second direction parallel to a side of the second lower semiconductor device, wherein the first direction is substantially collinear with the second direction. An upper semiconductor device is disposed on the first lower semiconductor device and the second lower semiconductor device and revealing a portion where the plurality of first conductive pillars and the plurality of second conductive pillars are disposed.Type: ApplicationFiled: November 7, 2024Publication date: March 20, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Kang Hsieh, Hung-Yi Kuo, Hao-Yi Tsai, Kuo-Lung Pan, Ting Hao Kuo, Yu-Chia Lai, Mao-Yen Chang, Po-Yuan Teng, Shu-Rong Chun
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Publication number: 20250077843Abstract: A behavior analysis system, comprising: a first electronic device configured to capture image data of a scene to obtain a first monitoring message; a computing unit, in communication with the first electronic device, comprising: an artificial intelligence module configured to receive the first monitoring message and detect a first behavior event from the first monitoring message; an event aggregation module configured to aggregate the first behavior event to generate an event aggregation report; and a language model configured to generate a behavior summary based on the event aggregation report; and a user equipment, in communication with the first electronic device and the computing unit, configured to display the behavior summary; wherein the behavior summary is in a form of natural language.Type: ApplicationFiled: November 28, 2023Publication date: March 6, 2025Inventors: Yu Chen CHANG, Chia-Yen CHANG, Nuo-Pai HSU, Ping-I CHOU
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Patent number: 12224001Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.Type: GrantFiled: November 30, 2022Date of Patent: February 11, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang, Li-Ping Huang, Yu-Fang Chen, Chun-Yen Tseng, Tzu-Feng Chang, Chun-Chieh Chang
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Publication number: 20130099089Abstract: A mould assembly with a heating device comprises: an upper mould with an upper joint surface, a lower mould, two conductive plates and two conductive wires. The lower mould includes a conductive layer, a lower joint surface which is formed on the conductive layer and faces the upper joint surface, an insulating surface which is formed on the conductive layer and faces in an opposite direction from the lower joint surface, an insulating formed on the insulating surface. The two conductive plates are disposed on the conductive layer of the lower mould. The two conductive wires are connected to the conductive plates and each have a resistivity lower than a resistivity of the conductive layer. The mould assembly with a heating device is low cost and capable of making the temperature distribution on the surface of the mould assembly more uniform.Type: ApplicationFiled: September 10, 2012Publication date: April 25, 2013Applicants: Kunshan Yurong Electronics Co., Ltd.Inventors: YU-YEN CHANG, Chung-Nan Liu
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Patent number: 7810645Abstract: A platform for securely mounting a wafer cassette holder thereon is provided which includes a wafer cassette holder that has a flat bottom surface and four sidewall panels, a platform that has a flat top surface larger than and for mating to the flat bottom surface of the wafer cassette holder, And a securing device mounted in the flat top surface of the platform juxtaposed to each side of the four sidewalls of the wafer cassette holder for preventing the holder from accidentally slipping off the platform, the securing device may include either a plurality of engagement pins that slidingly engages the wafer cassette holder for securely holding the holder on the platform, or a plurality of side panels mounted along the peripheral edge of the platform for preventing the holder from slipping off the platform.Type: GrantFiled: July 3, 2002Date of Patent: October 12, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Hung Huang, Ching-Chiang Chang, Yu-Yen Chang, Pei-Yi Kuo, Kuo-Chen Lin, Chung-Yi Lee
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Publication number: 20060127203Abstract: A cassette stocker and method of forming the same. The cassette stocker comprises a housing, at least one operation device, and a transferring device. The housing comprises a plurality of openings. The operation device is disposed corresponding to the openings and storing a cassette. The transferring device is disposed in the housing, retrieving and transferring the cassette stored in the operation device via the openings.Type: ApplicationFiled: May 4, 2005Publication date: June 15, 2006Inventors: Yu-Yen Chang, Hung-Wei Chen, Chien-Tien Lin
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Publication number: 20050036857Abstract: An automatic material handing system (AMHS). The AMHS comprises a rail, an overhead shuttle (OHS) and a stocker. The OHS moves on the rail. An in/out port (I/O port) is disposed in the stocker. The rail passes through the stocker and enters the I/O port. When the OHS is in the I/O port, a transport device places goods directly into the OHS.Type: ApplicationFiled: March 3, 2004Publication date: February 17, 2005Inventors: Hung-Wei Chen, Yu-Yen Chang
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Publication number: 20040265099Abstract: A conveyer system. The conveyer system includes a stocker and a conveyor. The stocker has a first position and a second position. The conveyor, with an Input/Output port, enters the stocker, wherein the Input/Output port is disposed between the first position and the second position.Type: ApplicationFiled: February 26, 2004Publication date: December 30, 2004Inventors: Yu-Yen Chang, Hung-Wei Chen
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Patent number: 6739820Abstract: Within both a stocker apparatus and a method for operating the stocker apparatus there is employed: (1) a minimum of six input/output ports; (2) an array of storage locations for storing an array of work in process (WIP) product units; and (3) a random access transportation means for transporting a work in process (WIP) product unit at least bidirectionally between the minimum of six input/output ports and a storage location within the array of storage locations. Within the stocker apparatus and the method, the minimum of six input/output ports provides for more efficient operation of the stocker apparatus.Type: GrantFiled: January 16, 2001Date of Patent: May 25, 2004Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Yu-Yen Chang, Kuo-Chen Lin
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Publication number: 20040004167Abstract: A platform for securely mounting a wafer cassette holder thereon is provided which includes a wafer cassette holder that has a flat bottom surface and four sidewall panels, a platform that has a flat top surface larger than and for mating to the flat bottom surface of the wafer cassette holder, and a securing means mounted in the flat top surface of the platform juxtaposed to each side of the four sidewalls of the wafer cassette holder for preventing the holder from accidentally slipping off the platform. The securing means may include either a plurality of engagement pins that slidingly engages the wafer cassette holder for securely holding the holder on the platform, or a plurality of side panels mounted along the peripheral edge of the platform for preventing the holder from slipping off the platform.Type: ApplicationFiled: July 3, 2002Publication date: January 8, 2004Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Hung Huang, Ching-Chiang Chang, Yu-Yen Chang, Pei-Yi Kuo, Kuo-Chen Lin, Chung-Yi Lee
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Patent number: 6536592Abstract: The SMIF pod includes a base having a cassette that may receive one or more wafers in preparation for transferring the wafers. The base includes a plurality of first openings formed on the side surfaces for a latch mechanism. The base includes a window formed on a surface of the base for an operator to read the state of the container. A box having second openings one to one corresponding to said first openings for the latch mechanism with latch member to penetrate through them while in the lock state. An indicator presents a first mark for indicating the locked state at the window or presents a second mark at the window for indicating the unlocked state.Type: GrantFiled: November 27, 2000Date of Patent: March 25, 2003Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Yu-Yen Chang, Kuo-Cheng Lin
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Patent number: 6516243Abstract: Within both a stocker apparatus and a method for operating the stocker apparatus there is employed, in addition to: (1) a minimum of one input/output port; (2) an array of storage locations for storing an array of work in process (WIP) product units; and (3) a random access transportation means for transporting a work in process (WIP) product unit at least bidirectionally between the minimum of one input/output port and a storage location within the array of storage locations; (4) a controller for controlling the random access transportation means. Within the stocker apparatus and the method, the controller is programmed such that upon unavailability of the minimum of one input/output port and upon concurrent receipt of a request to retrieve a work in process (WIP) product unit stored within the array of storage locations to reposition the requested work in process (WIP) product unit to a designated storage location within the array of storage locations where it may be manually retrieved.Type: GrantFiled: January 16, 2001Date of Patent: February 4, 2003Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Yu-Yen Chang, Kuo-Chen Lin
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Publication number: 20020095223Abstract: Within both a stocker apparatus and a method for operating the stocker apparatus there is employed, in addition to: (1) a minimum of one input/output port; (2) an array of storage locations for storing an array of work in process (WIP) product units; and (3) a random access transportation means for transporting a work in process (WIP) product unit at least bidirectionally between the minimum of one input/output port and a storage location within the array of storage locations; (4) a controller for controlling the random access transportation means. Within the stocker apparatus and the method, the controller is programmed such that upon unavailability of the minimum of one input/output port and upon concurrent receipt of a request to retrieve a work in process (WIP) product unit stored within the array of storage locations to reposition the requested work in process (WIP) product unit to a designated storage location within the array of storage locations where it may be manually retrieved.Type: ApplicationFiled: January 16, 2001Publication date: July 18, 2002Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Yen Chang, Kuo-Chen Lin
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Publication number: 20020094256Abstract: Within both a stocker apparatus and a method for operating the stocker apparatus there is employed: (1) a minimum of six input/output ports; (2) an array of storage locations for storing an array of work in process (WIP) product units; and (3) a random access transportation means for transporting a work in process (WIP) product unit at least bidirectionally between the minimum of six input/output ports and a storage location within the array of storage locations. Within the stocker apparatus and the method, the minimum of six input/output ports provides for more efficient operation of the stocker apparatus.Type: ApplicationFiled: January 16, 2001Publication date: July 18, 2002Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Yen Chang, Kuo-Chen Lin