Patents by Inventor Yu-Yen Chen

Yu-Yen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240395550
    Abstract: A method for fabricating a semiconductor device is provided. The method includes coating a photoresist film over a target layer over a semiconductor substrate; performing a lithography process to pattern the photoresist film into a photoresist layer; performing a directional ion bombardment process to the photoresist layer along a direction tilted with respect to a normal direction of the semiconductor substrate, such that a carbon atomic concentration in the photoresist layer is increased; and etching the target layer using the photoresist layer as an etch mask.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Tien SHEN, Chih-Kai YANG, Hsiang-Ming CHANG, Chun-Yen CHANG, Ya-Hui CHANG, Wei-Ting CHIEN, Chia-Cheng CHEN, Liang-Yin CHEN
  • Patent number: 12154965
    Abstract: The present disclosure relates to an integrated circuit (IC) chip including a memory cell with a carrier barrier layer for threshold voltage tunning. The memory cell may, for example, include a gate electrode, a ferroelectric structure, and a semiconductor structure. The semiconductor structure is vertically stacked with the gate electrode and the ferroelectric structure, and the ferroelectric structure is between the gate electrode and the semiconductor structure. A pair of source/drain electrodes is laterally separated and respectively on opposite sides of the gate electrode, and a carrier barrier layer separates the source/drain electrodes from the semiconductor structure.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: November 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Rainer Yen-Chieh Huang, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240387685
    Abstract: The present disclosure relates to an integrated circuit (IC) chip including a memory cell with a carrier barrier layer for threshold voltage tuning. The memory cell may, for example, include a gate electrode, a ferroelectric structure, and a semiconductor structure. The semiconductor structure is vertically stacked with the gate electrode and the ferroelectric structure, and the ferroelectric structure is between the gate electrode and the semiconductor structure. A pair of source/drain electrodes is laterally separated and respectively on opposite sides of the gate electrode, and a carrier barrier layer separates the source/drain electrodes from the semiconductor structure.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Rainer Yen-Chieh Huang, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 12148809
    Abstract: The present invention provides a layout pattern of static random access memory, comprising a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: November 19, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang, Chien-Hung Chen, Li-Ping Huang, Chun-Yen Tseng
  • Publication number: 20240379075
    Abstract: An anti-dizziness display method, a processing device, and an information display system are proposed. The information display system is configured to display on a mobile vehicle and includes a first display, a transportation environment information acquisition device, and a processing device. The transportation environment information acquisition device is configured to obtain transportation environment information of the mobile vehicle. The processing device is configured to perform the following operations. A visual feedback magnitude is determined according to the transportation environment information, and the visual feedback magnitude varies in response to variation of the transportation environment information. A display image of the first display is controlled according to the visual feedback magnitude, so that the display image of the first display changes in response to the variation in the transportation environment information.
    Type: Application
    Filed: March 6, 2024
    Publication date: November 14, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Hong-Ming Dai, Ya-Rou Hsu, Chien-Ju Lee, Chun-Yen Huang, Kuan-Ting Chen, Yu-Hsiang Tsai, Chia-Hsun Tu
  • Publication number: 20240345211
    Abstract: An electronic device and a control method thereof are provided. The electronic device includes a DSP (Digital Signal Processor). The DSP receives a digital signal. The digital signal includes a plurality of frames. The DSP divides the plurality of frames into a vital group and a non-vital group according to a criterion. The DSP compares a total number of frames of the vital group with a threshold value. In response to the total number of frames of the vital group being greater than the threshold value, the DSP may calculate signal strength of the vital group.
    Type: Application
    Filed: June 8, 2023
    Publication date: October 17, 2024
    Inventors: Chuan Yen KAO, Yu Wen HUANG, Wei Rong TSENG, Yao Tsung CHANG, Yin Yu CHEN
  • Publication number: 20240349515
    Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region and a second cell region and a diffusion region on the substrate extending through the first cell region and the second cell region. Preferably, the diffusion region includes a first H-shape and a second H-shape according to a top view.
    Type: Application
    Filed: June 27, 2024
    Publication date: October 17, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Shu-Ru Wang, Yu-Tse Kuo, Chang-Hung Chen, Yi-Ting Wu, Shu-Wei Yeh, Ya-Lan Chiou, Chun-Hsien Huang
  • Patent number: 12120293
    Abstract: A video coding system generating candidates for Merge Mode with Motion Vector Difference (MMVD) with reduced resource usage is provided. The system receives data to be encoded or decoded as a current block of a current picture of a video. The system identifies multiple MMVD candidates for different offset positions based on a merge candidate of the current block. The system generates reference samples for the identified MMVD candidates. The system reconstructs the current block or encodes the current block into a bitstream by using the generated reference samples. The system processes the MMVD candidates in separate groups: a first group of vertical MMVD candidates and a second group of horizontal MMVD candidates. The system generates the reference samples for the identified MMVD candidates by applying a vertical filter to source reference samples of horizontal MMVD candidates and then applying a horizontal filter to outputs of the vertical filter.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: October 15, 2024
    Assignee: MediaTek Inc.
    Inventors: Cheng-Yen Chuang, Man-Shu Chiang, Chun-Chia Chen, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang
  • Patent number: 12112516
    Abstract: A non-intrusive detection method for detecting at least one pop-up window button of the pop-up window includes the following steps: retrieving a screen image on a display device; comparing the screen image with a preset screen image and generating a differential image area according the screen image and the preset screen image; determining the differential image area as the pop-up window when the differential image area is greater than an image area threshold value; selecting a plurality of contour lengths of the pop-up window matching up with a contour length threshold value by Canny edge detector; and analyzing the contour lengths according to Douglas-Peucker algorithm and an amount of endpoints to generate a contour edge corresponding to the pop-up window button.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: October 8, 2024
    Assignee: ADLINK Technology Inc.
    Inventors: Chien-Chung Lin, Wei-Jyun Tu, Yu-Yen Chen
  • Publication number: 20240329361
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a circuit assembly. The movable assembly is configured to connect an optical element, the movable assembly is movable relative to the fixed assembly, and the optical element has an optical axis. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The circuit assembly includes a plurality of circuits and is affixed to the fixed assembly.
    Type: Application
    Filed: June 7, 2024
    Publication date: October 3, 2024
    Inventors: Sin-Hong LIN, Yung-Ping YANG, Wen-Yen HUANG, Yu-Cheng LIN, Kun-Shih LIN, Chao-Chang HU, Yung-Hsien YEH, Mao-Kuo HSU, Chih-Wei WENG, Ching-Chieh HUANG, Chih-Shiang WU, Chun-Chia LIAO, Chia-Yu CHANG, Hung-Ping CHEN, Wei-Zhong LUO, Wen-Chang LIN, Shou-Jen LIU, Shao-Chung CHANG, Chen-Hsin HUANG, Meng-Ting LIN, Yen-Cheng CHEN, I-Mei HUANG, Yun-Fei WANG, Wei-Jhe SHEN
  • Patent number: 12100789
    Abstract: A display device, including a circuit substrate, a light-emitting layer, a quarter-wave plate, and a band-pass polarizing layer, is provided. The light-emitting layer is disposed on the circuit substrate and has light-emitting structures, which are electrically connected to the circuit substrate and include first light-emitting structures, which have a first main light-emitting wavelength. The quarter-wave plate is disposed in overlap with the light-emitting structures and is located between the band-pass polarizing layer and the light-emitting layer. The band-pass polarizing layer includes at least one first band-pass polarizing pattern, which have a first absorption axis. The first wavelength range is the first main light-emitting wavelength±10 nm. An average transmittance of the first band-pass polarizing patterns to light with a wavelength outside the first wavelength range and a polarization direction parallel to the first absorption axis is less than 20%.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: September 24, 2024
    Assignee: Coretronic Corporation
    Inventors: Ping-Yen Chen, Wen-Chun Wang, Chung-Yang Fang, Yu-Fan Chen
  • Publication number: 20240312014
    Abstract: In an automated detection system for acute ischemic stroke, a preprocessor performs registration on a whole-brain image and a standard-brain spatial template to extract individual brain region masks from the whole-brain image. A deep learning encoder performs feature extraction on the whole-brain image and the individual brain region masks, thereby converting the whole-brain image into 2D whole-brain slice images. A first processor maps the individual brain masks onto the whole-brain slice images for registration, thereby generating sets of brain region slice images. A second processor computes the stroke-related weight values of the slice images of each of the sets of brain region slice images and sums the weight values to obtain the characteristic value of each brain region. A disparity-aware classifier determines whether any brain region has acute ischemic stroke according to the characteristic value of each brain region.
    Type: Application
    Filed: June 14, 2023
    Publication date: September 19, 2024
    Applicants: National Yang Ming Chiao Tung University, Kaohsiung Chang Gung Memorial Hospital
    Inventors: Yong-Sheng CHEN, Wei-Che Lin, Shih-Yen Lin, Hsiang-Chun Yang, YU-LIN YEH, Evelyne Calista, Pi-Ling Chiang
  • Publication number: 20240297138
    Abstract: Package structures and methods for manufacturing the same are provided. The package structure includes a first substrate and through vias formed through the first substrate. The package further includes redistribution layers formed over the first substrate and connected to the through vias and a first pillar layer formed over the redistribution layers. The package further includes a first barrier layer formed over the first pillar layer and a first cap layer formed over the first barrier layer. The package further includes an underfill layer formed over the redistribution layers and surrounding the first pillar layer, the first barrier layer, and the first cap layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first sidewall surface of the first pillar layer and a second sidewall surface of the first cap layer.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hung CHEN, Yu-Nu HSU, Chun-Chen LIU, Heng-Chi HUANG, Chien-Chen LI, Shih-Yen CHEN, Cheng-Nan HSIEH, Kuo-Chio LIU, Chen-Shien CHEN, Chin-Yu KU, Te-Hsun PANG, Yuan-Feng WU, Sen-Chi CHIANG
  • Patent number: 12063791
    Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region and a second cell region and a diffusion region on the substrate extending through the first cell region and the second cell region. Preferably, the diffusion region includes a first H-shape and a second H-shape according to a top view.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: August 13, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Shu-Ru Wang, Yu-Tse Kuo, Chang-Hung Chen, Yi-Ting Wu, Shu-Wei Yeh, Ya-Lan Chiou, Chun-Hsien Huang
  • Publication number: 20240251568
    Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.
    Type: Application
    Filed: April 4, 2024
    Publication date: July 25, 2024
    Inventors: Tai-Yen Peng, Tsung-Hsien Chang, Yu-Shu Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Chung-Te Lin
  • Patent number: 12044721
    Abstract: A scan chain designing method includes: obtaining test points according to a gate-level netlist; determining integers M and N, wherein M and N are no greater than an amount X of the test points; selecting M and N test points to be a first and second set test points according to a priority; obtaining a first test coverage and a first test pattern count according to the first set test points and obtaining a second test coverage and a second test pattern count according to the second set test points; obtaining a predicted test coverage curve according to the first and second test coverages; determining an optimum amount O according to the predicted test coverage curve, the first and second test pattern counts, wherein O is no greater than X; and selecting O test points to arrange a scan chain according to the priority and the optimum amount O.
    Type: Grant
    Filed: October 25, 2022
    Date of Patent: July 23, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shiou Wen Wang, Yu Yen Yang, Ying-Yen Chen
  • Patent number: 11881037
    Abstract: An automatically detecting method for time-varying text region of interest is disclosed. The automatically detecting method is adapted to an image processing unit of an information retrieval system, to detect a time-varying text region of interest having specific characters or character set as unit on an operation screen of a manufacturing machine, a processing machine or other equipment; furthermore, the automatically detecting method can be performed based on presence or absence of the historical screen data, and union of the detected region proposals for the time-varying text region of interest, to obtain an automatically labeled and selected time-varying text region of interest. According to the automatically detecting method, the user only needs to confirm whether the required data are labeled and selected, so it is more convenient for the user to setting data, and greatly helpful to reduce the setting time and correctly detect the required information.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: January 23, 2024
    Assignee: ADLINK TECHNOLOGY INC.
    Inventors: Chien-Chung Lin, Wei-Jyun Tu, Yu-Yen Chen
  • Publication number: 20230241679
    Abstract: Reactor configurations may include one or more staged inlets and/or one or more staged outlets for gaseous and solid feedstocks. In one embodiment of the present disclosure, a reactor design for gas-solid reaction with one or more additional outlet for gas and/or solid phase is provided. In yet another embodiment, the design for a gas-solid reactor with one side inlet and two outlets for gas phase is described. In one embodiment, a reactor design with pairs of inlet and outlet for both gas and solid phase is provided. In another embodiment, a reactor design with one or more side inlets but only one outlet for gas phase is provided. In yet another embodiment, a reactor design with two inlets at the top/bottom of reactor and two side outlets for gaseous phase is described. In yet another embodiment, a reactor design with one or more side inlets and outlets for both gas and solid phases is provided.
    Type: Application
    Filed: June 29, 2021
    Publication date: August 3, 2023
    Inventors: Liang-Shih Fan, Andrew Tong, Liang Zeng, Yitao Zhang, Frank Kong, Yu-Yen Chen
  • Patent number: 11656604
    Abstract: Provided is a cutting speed planning system including a graphic preprocessing engine, a first speed planning engine, an included angle calculation engine, a second speed planning engine and a speed determination engine. The graphic preprocessing engine substitutes a simplified cutting route for a plurality of short straight paths of a graphic path. The first speed planning engine calculates a reasonable maximum cutting speed of each cutting route. The included angle calculation engine calculates the included angle between two adjacent ones of the cutting routes. The second speed planning engine adjusts the terminal cutting speed and the initial cutting speed of the cutting routes. The speed determination engine performs speed planning on the cutting routes according to digital control system period time. A cutting speed planning method and a non-transitory storage medium are further provided.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: May 23, 2023
    Assignee: ADLINK TECHNOLOGY INC.
    Inventors: Wei-Li Chuang, Wei-Fan Chen, Yu-Yen Chen
  • Publication number: 20220414390
    Abstract: A non-intrusive detection method for detecting at least one pop-up window button of the pop-up window includes the following steps: retrieving a screen image on a display device; comparing the screen image with a preset screen image and generating a differential image area according the screen image and the preset screen image; determining the differential image area as the pop-up window when the differential image area is greater than an image area threshold value; selecting a plurality of contour lengths of the pop-up window matching up with a contour length threshold value by Canny edge detector; and analyzing the contour lengths according to Douglas-Peucker algorithm and an amount of endpoints to generate a contour edge corresponding to the pop-up window button.
    Type: Application
    Filed: October 11, 2021
    Publication date: December 29, 2022
    Inventors: CHIEN-CHUNG LIN, WEI-JYUN TU, YU-YEN CHEN