Patents by Inventor Yu-Yen Huang
Yu-Yen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984419Abstract: Package structures and methods for manufacturing the same are provided. The package structure includes a first bump structure formed over a first substrate. The first bump structure includes a first pillar layer formed over the first substrate and a first barrier layer formed over the first pillar layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first edge of the first pillar layer. The package structure further includes a second bump structure bonded to the first bump structure through a solder joint. In addition, the second bump structure includes a second pillar layer formed over a second substrate and a second barrier layer formed over the second pillar layer. The first protruding portion of the first barrier layer is spaced apart from the solder joint.Type: GrantFiled: July 26, 2022Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Hung Chen, Yu-Nu Hsu, Chun-Chen Liu, Heng-Chi Huang, Chien-Chen Li, Shih-Yen Chen, Cheng-Nan Hsieh, Kuo-Chio Liu, Chen-Shien Chen, Chin-Yu Ku, Te-Hsun Pang, Yuan-Feng Wu, Sen-Chi Chiang
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Patent number: 11979613Abstract: Encoding methods and apparatuses include receiving input video data of a current block in a current picture and applying a Cross-Component Adaptive Loop Filter (CCALF) processing on the current block based on cross-component filter coefficients to refine chroma components of the current block according to luma sample values. The method further includes signaling two Adaptive Loop Filter (ALF) signal flags and two CCALF signal flags in an Adaptation Parameter Set (APS) with an APS parameter type equal to ALF or parsing two ALF signal flags and two CCALF signal flags from an APS with an APS parameter type equal to ALF, signaling or parsing one or more Picture Header (PH) CCALF syntax elements or Slice Header (SH) CCALF syntax elements, wherein both ALF and CCALF signaling are present either in a PH or SH, and encoding or decoding the current block in the current picture.Type: GrantFiled: June 28, 2022Date of Patent: May 7, 2024Assignee: HFI INNOVATION INC.Inventors: Ching-Yeh Chen, Olena Chubach, Chen-Yen Lai, Tzu-Der Chuang, Chih-Wei Hsu, Yu-Wen Huang
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Publication number: 20240145381Abstract: In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.Type: ApplicationFiled: January 9, 2024Publication date: May 2, 2024Inventors: Shin-Yi Yang, Hsin-Yen Huang, Ming-Han Lee, Shau-Lin Shue, Yu-Chen Chan, Meng-Pei Lu
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Publication number: 20240133421Abstract: An electronic device includes a monitor stand, a hinge mechanism, and an operation element. The hinge mechanism includes a back plate, a speed reduction assembly, and a friction assembly. The back plate is fixed to the monitor stand. The speed reduction assembly includes an input plate and a speed reduction member. The speed reduction member is arranged on the input plate. The friction assembly is arranged between the back plate and the input plate. The operation element is connected to the speed reduction member. A rotation center of the operation element coincides with an axis of the back plate and the speed reduction member are coaxially arranged.Type: ApplicationFiled: January 17, 2023Publication date: April 25, 2024Inventors: Chih-Wei KUO, Yu-Chun HUNG, Che-Yen CHOU, Chen-Wei TSAI, Hsiang-Wen HUANG
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Publication number: 20240112924Abstract: An integrated circuit package including integrated circuit dies with slanted sidewalls and a method of forming are provided. The integrated circuit package may include a first integrated circuit die, a first gap-fill dielectric layer around the first integrated circuit die, a second integrated circuit die underneath the first integrated circuit die, and a second gap-fill dielectric layer around the second integrated circuit die. The first integrated circuit die may include a first substrate, wherein a first angle is between a first sidewall of the first substrate and a bottom surface of the first substrate, and a first interconnect structure on the bottom surface of the first substrate, wherein a second angle is between a first sidewall of the first interconnect structure and the bottom surface of the first substrate. The first angle may be larger than the second angle.Type: ApplicationFiled: January 5, 2023Publication date: April 4, 2024Inventors: Hsu-Hsien Chen, Chen-Shien Chen, Ting Hao Kuo, Chi-Yen Lin, Yu-Chih Huang
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Publication number: 20240105664Abstract: A package structure includes a first RDL, an adhesive layer and a first electronic component. Upper bumps and conductive pads are provided on a first upper surface and a first lower surface of the first RDL, respectively. The adhesive layer is located on the first upper surface of the first RDL and surrounds the upper bumps. The first electronic component is mounted on the adhesive layer and includes conductors which are visible from an active surface of the first electronic component and joined to the upper bumps, the active surface of the first electronic component faces toward the first upper surface of the first RDL. Two adhesive surfaces of the adhesive layer are adhered to the first upper surface of the first RDL and the active surface of the first electronic component, respectively.Type: ApplicationFiled: August 16, 2023Publication date: March 28, 2024Inventors: Yu-Chung Huang, Hsin-Yen Tsai, Fa-Chung Chen, Cheng-Fan Lin, Chen-Yu Wang
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Patent number: 11943935Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.Type: GrantFiled: September 26, 2022Date of Patent: March 26, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yen Tseng, Shu-Ru Wang, Yu-Tse Kuo, Chang-Hung Chen, Yi-Ting Wu, Shu-Wei Yeh, Ya-Lan Chiou, Chun-Hsien Huang
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Patent number: 11939431Abstract: The present invention relates to a composition comprising an amino acid-modified polymer, a carboxypolysaccharide, and may further include a metal ion for anti-adhesion and vector application. More specifically, the invention relates to a thermosensitive composition having enhanced mechanical and improved water-erosion resistant properties for efficiently preventing tissue adhesions and can serve as a vector with bio-compatible, bio-degradable/absorbable, and in-vivo sustainable properties.Type: GrantFiled: April 23, 2021Date of Patent: March 26, 2024Assignee: PROVIEW-MBD BIOTECH CO., LTD.Inventors: Yu-Chia Chang, Yunn-Kuen Chang, Wen-Yen Huang, Ging-Ho Hsiue, Hsieh-Chih Tsai, Shuian-Yin Lin, Nai-Sheng Hsu, Tzu-Yu Lin
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Patent number: 11944017Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.Type: GrantFiled: May 5, 2023Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tai-Yen Peng, Yu-Shu Chen, Chien Chung Huang, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
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Patent number: 11939432Abstract: Synthetic amino acid-modified polymers and methods of making the same and using the same are disclosed. The synthetic amino acid-modified polymers possess distinct thermosensitive, improved water-erosion resistant, and enhanced mechanical properties, and are suitable of reducing or preventing formation of postoperative tissue adhesions. Additionally, the amino acid-modified polymers can also be used as a vector to deliver pharmaceutically active agents.Type: GrantFiled: April 23, 2021Date of Patent: March 26, 2024Assignee: PROVIEW-MBD BIOTECH CO., LTD.Inventors: Yu-Chia Chang, Yunn-Kuen Chang, Wen-Yen Huang, Ging-Ho Hsiue, Hsieh-Chih Tsai, Shuian-Yin Lin, Nai-Sheng Hsu, Tzu-Yu Lin
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Publication number: 20240099150Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
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Patent number: 11915755Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.Type: GrantFiled: January 20, 2022Date of Patent: February 27, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yen Tseng, Yu-Tse Kuo, Shu-Ru Wang, Chun-Hsien Huang, Hsin-Chih Yu, Meng-Ping Chuang, Li-Ping Huang, Yu-Fang Chen
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Publication number: 20230333327Abstract: The present disclosure relates to a method of making a lensed connector in which a glass ferrule has holes within the body of the glass ferrule, and the glass ferrule is subsequently processed to form lens structures along the ferrule.Type: ApplicationFiled: June 22, 2023Publication date: October 19, 2023Inventors: Nicholas Francis Borrelli, Davide Domenico Fortusini, Yu-Yen Huang, Shawn Michael O'Malley, Georges Roussos, Joseph Francis Schroeder, III, Jun Yang, Lei Yuan
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Patent number: 11719891Abstract: The present disclosure relates to a method of making a lensed connector in which a glass ferrule has holes within the body of the glass ferrule, and the glass ferrule is subsequently processed to form lens structures along the ferrule.Type: GrantFiled: July 7, 2021Date of Patent: August 8, 2023Assignee: Corning Research & Development CorporationInventors: Nicholas Francis Borrelli, Davide Domenico Fortusini, Yu-Yen Huang, Shawn Michael O'Malley, Georges Roussos, Joseph Francis Schroeder, III, Jun Yang, Lei Yuan
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Publication number: 20220043218Abstract: The present disclosure relates to a method of making a lensed connector in which a glass ferrule has holes within the body of the glass ferrule, and the glass ferrule is subsequently processed to form lens structures along the ferrule.Type: ApplicationFiled: July 7, 2021Publication date: February 10, 2022Inventors: Nicholas Francis Borrelli, Davide Domenico Fortusini, Yu-Yen Huang, Shawn Michael O'Malley, Georges Roussos, Joseph Francis Schroeder, III, Jun Yang, Lei Yuan
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Publication number: 20130075318Abstract: An apparatus for isolating rare cells from a blood sample is disclosed. The apparatus includes a reservoir for supplying the blood sample and a pump for receiving the blood sample. The apparatus also includes a microchip and a set of magnets. The microchip has a microchannel formed between the microchip and a glass slide. The microchannel is connected between the reservoir and the pump to allow the blood sample to flow from the reservoir to the pump. The set of magnets is located adjacent to the glass slide to form a magnetic gradient along the glass slide on which rare cells can be isolated from the blood sample.Type: ApplicationFiled: September 23, 2011Publication date: March 28, 2013Inventors: Xiaojing Zhang, Yu-Yen Huang, Ting Shen, Kazunori Hoshino, Jonathan Uhr, Eugene Frenkel