Patents by Inventor Yu-Yi CHIANG

Yu-Yi CHIANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240194591
    Abstract: A package structure includes a thermal dissipation structure including a substrate, a first encapsulant laterally covering the substrate, a die disposed on the substrate and including a sensing region, a second encapsulant laterally covering the die, and a redistribution structure disposed on the die and the second encapsulant. An outer sidewall of the second encapsulant is laterally offset from an outer sidewall of the first encapsulant. The die is electrically coupled to the substrate through the redistribution structure, and the redistribution structure includes a hollow region overlying the sensing region of the die.
    Type: Application
    Filed: February 20, 2024
    Publication date: June 13, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Patent number: 11994970
    Abstract: A diagnostic system applied to an electronic equipment with a plurality of hardware devices is provided. The hardware devices include a display and a processor, the diagnostic system is executed by the processor to diagnose the hardware devices. The diagnostic system includes a diagnostic test interface, which is displayed on the display and includes a plurality of hardware items corresponding to the hardware devices. Each of the hardware items links to the hardware devices. When at least one of the hardware items is triggered, the processor executes the diagnostic item of the hardware device corresponding to the triggered hardware item.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: May 28, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Kun-Hsin Chiang, Hsin-Hui Huang, Wei-Hsian Chang, Wen-Yen Hsieh, Ming-Yi Huang, Yu-Chieh Chang, Tang-Hui Liao, Chih-Wei Kuo
  • Publication number: 20240120410
    Abstract: A semiconductor structure includes a semiconductor epitaxial layer, a first semiconductor well, a second semiconductor well, a source doped region, a gate structure and a drain structure. The semiconductor epitaxial layer includes a first side and a second side opposite to the first side. The first semiconductor well is located on the first side of the semiconductor epitaxial layer. The second semiconductor well is located on the second side of the semiconductor epitaxial layer. The source doped region is located in the first semiconductor well. The gate structure overlaps the first semiconductor well and the source doped region on the first side of the semiconductor epitaxial layer. The drain structure includes a semiconductor substrate. The second side of the semiconductor epitaxial layer outside the second semiconductor well includes a connecting surface. The connecting surface of the semiconductor epitaxial layer is connected to the semiconductor substrate.
    Type: Application
    Filed: February 16, 2023
    Publication date: April 11, 2024
    Inventors: Yu-Tsu LEE, Yan-Ru CHEN, Chao-Yi CHANG, Kuang-Hao CHIANG
  • Patent number: 11929318
    Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20240081077
    Abstract: A transistor includes a first semiconductor layer, a second semiconductor layer, a semiconductor nanosheet, a gate electrode and source and drain electrodes. The semiconductor nanosheet is physically connected to the first semiconductor layer and the second semiconductor layer. The gate electrode wraps around the semiconductor nanosheet. The source and drain electrodes are disposed at opposite sides of the gate electrode. The first semiconductor layer surrounds the source electrode, the second semiconductor layer surrounds the drain electrode, and the semiconductor nanosheet is disposed between the source and drain electrodes.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., National Yang Ming Chiao Tung University
    Inventors: Po-Tsun Liu, Meng-Han Lin, Zhen-Hao Li, Tsung-Che Chiang, Bo-Feng Young, Hsin-Yi Huang, Sai-Hooi Yeong, Yu-Ming Lin
  • Publication number: 20230201129
    Abstract: Disclosed herein are electrospun fibrous matrix and its production method. The method mainly includes the steps of, mixing a first polymer and a drug to form a first mixture, and sonicating the first mixture until a plurality of microparticles are formed with the drug encapsulated therein; and mixing the plurality of microparticles with a second polymer to form a second mixture, subjecting the second mixture to a wet electrospinning process to form the electrospun fibrous matrix. The thus-produced electrospun fibrous matrix is characterized by having a plurality of first and second fibrils woven together, in which each second fibril has a plurality of drug-encapsulated microparticles independently integrated and disposed along the longitudinal direction of the second fibril. Also encompassed in the present disclosure is a method for treating a wound of a subject. The method includes applying the present electrospun fibrous matrix to the wound of the subject to accelerate wound healing.
    Type: Application
    Filed: December 28, 2021
    Publication date: June 29, 2023
    Applicant: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Ping-Ching WU, Cheng-Hsin CHUANG, Po-Heng CHEN, Yu-Yi CHIANG