Abstract: A package structure is provided, and includes a first bonding film formed on a first substrate, and a first alignment mark formed in the first bonding film. The first alignment mark includes a plurality of first patterns spaced apart from each other. The package structure includes a second bonding film formed on a second substrate and bonded to the first bonding film, and a second alignment mark formed in the second bonding film. The second alignment mark includes a plurality of second patterns spaced apart from each other. In a top view, the first alignment mark is spaced apart from the second alignment mark, and the distance between adjacent first patterns is less than the distance between the first alignment mark and the second alignment mark.

Abstract: A barrier layer is formed in a portion of a thickness of sidewalls in a recess prior to formation of an interconnect structure in the recess. The barrier layer is formed in the portion of the thickness of the sidewalls by a plasma-based deposition operation, in which a precursor reacts with a silicon-rich surface to form the barrier layer. The barrier layer is formed in the portion of the thickness of the sidewalls in that the precursor consumes a portion of the silicon-rich surface of the sidewalls as a result of the plasma treatment. This enables the barrier layer to be formed in a manner in which the cross-sectional width reduction in the recess from the barrier layer is minimized while enabling the barrier layer to be used to promote adhesion in the recess.

Abstract: A semiconductor structure includes a metal gate structure including a gate dielectric layer and a gate electrode, a conductive layer disposed on the gate electrode, and a gate contact disposed on the conductive layer. The conductive layer extends from a position below a top surface of the metal gate structure to a position above the top surface of the metal gate structure. The gate electrode includes at least a first metal, and the conductive layer includes at least the first metal and a second metal different from the first metal. Laterally the conductive layer is fully between opposing sidewalls of the metal gate structure.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

Abstract: A method of obtaining brightness information of a display panel having a plurality of pixels includes steps of: obtaining positioning information indicating positions of the plurality of pixels on a test picture; lighting up the plurality of pixels and capturing the test picture; measuring the plurality of pixels according to the positioning information, to obtain a light intensity distribution of each of the plurality of pixels in the test picture; and calculating the brightness information of each of the plurality of pixels according to the light intensity distribution.

Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic structure and a wall structure surrounding the electronic structure are disposed on a carrier structure, a heat conducting layer is formed on the electronic structure, and the wall structure and the heat conducting layer are covered by a heat dissipation element. Therefore, a thermal stress can be effectively dispersed by the arrangement of the wall structure, such that a warpage of the electronic structure and a heat dissipation body can be effectively controlled.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

Abstract: A light-emitting device, including: a semiconductor stack generating a first light; and a filter formed on the stack, including a first surface facing the stack and a second surface opposite to the first surface. The filter includes pairs of layers with different refractive indexes alternately stacked, and a portion of the first light is transmitted by the filter. The light emitting device emits a second light including the portion of the first light, and the second light includes a first directional part with a first FWHM and a second directional part with a second FWHM. The first directional part has a first angle with a normal direction of the second surface in a range of 45-90 degrees, the second directional part has a second angle with the normal direction of the second surface in a range of 0-30 degrees, and the second FWHM is smaller than the first FWHM.