Abstract: A coupled physiological signal measuring device is provided. The coupled physiological signal measuring device includes at least two measuring electrodes, a signal processing unit and a multiplex feedback circuit unit. The measuring electrodes are used to obtain a real-time physiological signal through measurement. The signal processing unit includes a discharge control element. If an electrostatic surge of the real-time physiological signal meets a condition, a discharge control signal is outputted. The multiplex feedback circuit unit is used to discharge the measuring electrodes according to the discharge control signal.

Abstract: A physiological signal measurement system, a physiological signal measurement method, and a mobile device protective case are provided. The physiological signal measurement system includes a first electrode, a second electrode, a reference electrode, an impedance front-end circuit module and a dynamic signal matching module. The first electrode, the second electrode and the reference electrode are used to obtain a first sensing signal and a second sensing signal. The impedance front-end circuit module is used to detect a first impedance of the first electrode and a second impedance of the second electrode, and obtain an original differential signal according to the first sensing signal and the second sensing signal. The dynamic signal matching module is used to obtain a calibration sequence according to the first impedance, the second impedance and the original differential signal, and obtain a compensated calibration sequence according to the calibration sequence and the original differential signal.

Abstract: An organic semiconductor mixture and an organic optoelectronic device containing the same are provided. A n-type organic semiconductor compound in the organic semiconductor mixture has a novel chemical structure so that the mixture has good thermal stability and property difference during batch production is also minimized. The organic semiconductor mixture is applied to organic optoelectronic devices such as organic photovoltaic devices for providing good energy conversion efficiency while in use.

Abstract: A semiconductor device includes a gate, a semiconductor structure, a gate insulating layer, a first source/drain feature and a second source/drain feature. The gate insulating layer is located between the gate and the semiconductor structure. The semiconductor structure includes at least one first metal oxide layer, a first oxide layer, and at least one second metal oxide layer. The first oxide layer is located between the first metal oxide layer and the second metal oxide layer. The first source/drain feature and the second source/drain feature are electrically connected with the semiconductor structure.

Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Abstract: A fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a plurality of fin structures above a substrate, an isolation structure over the substrate and between the fin structures, and a gate structure formed over the fin structure. The FinFET device structure includes a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The FinFET device structure also includes a metal silicide layer over the S/D structure, and the metal silicide layer is in contact with the isolation structure.

Abstract: Some embodiments relate to a thin film transistor comprising an active layer over a substrate. An insulator is stacked with the active layer. A gate electrode structure is stacked with the insulator and includes a gate material layer having a first work function and a first interfacial layer. The first interfacial layer is directly between the insulator and the gate material layer, wherein the gate electrode structure has a second work function that is different from the first work function.

Abstract: A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.

Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.

Abstract: Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.

Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.

Abstract: An organic semiconducting compound and an organic photoelectric component containing the same are provided. The organic semiconducting compound has a novel chemical structure to make the organic semiconducting compound have good response to the infrared light. The organic semiconducting compound can be applied to the organic photoelectric components such as organic photodetector (OPD), organic photovoltaic (OPV) cell, and organic field-effect transistor (OFET). Thus, the organic photoelectric components have better light absorption range and photoelectric response while in use.

Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.

Abstract: A method for performing a chemical mechanical polishing (CMP) is disclosed. The method includes supplying a slurry onto a polishing pad, holding a first wafer against the polishing pad by a first polishing head, holding a second wafer against the polishing pad by a second polishing head, and rotating the polishing pad.

Abstract: A chemical mechanical polishing system includes a platen, a slurry introduction device and at least one polishing head. The platen is configured to allow a polishing pad to be disposed thereon. The slurry introduction device is configured to supply slurry onto the polishing pad. The polishing head includes a main body and at least one grinding piece. The main body has an accommodation space for accommodating a wafer. The grinding piece is disposed on the main body. The grinding piece has a grinding surface configured to grind against the polishing pad.

Abstract: A chemical mechanical polishing system includes a platen, a slurry introduction device and at least one polishing head. The platen is configured to allow a polishing pad to be disposed thereon. The slurry introduction device is configured to supply slurry onto the polishing pad. The polishing head includes a main body and at least one grinding piece. The main body has an accommodation space for accommodating a wafer. The grinding piece is disposed on the main body. The grinding piece has a grinding surface configured to grind against the polishing pad.