Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.

Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.

Abstract: A resonant asymmetrical half-bridge flyback power converter includes: a first transistor and a second transistor switching a transformer coupled to a capacitor for generating an output power; a voltage divider coupled to an auxiliary winding of the transformer; a differential sensing circuit which includes a first terminal and a second terminal coupled to the voltage divider to sense an auxiliary signal generated by the auxiliary winding for generating a peak signal and a demagnetization-time signal; and a PWM control circuit configured to generate a first PWM signal and a second PWM signal in accordance with the peak signal and the demagnetization-time signal, for controlling the first transistor and the second transistor respectively; wherein a period of an enabling state of the demagnetization-time signal is correlated to the output power level; wherein the peak signal is related to a quasi-resonance of the transformer after the transformer is demagnetized.

Abstract: An image recognition method includes the steps of: receiving a captured image; acquiring a focusing zone image from a portion of the captured image; processing the captured image and/or the focusing zone image and then making the two images into a batch of image information; and executing an image analysis procedure on the batch of image information to generate an analysis result.

Abstract: Package devices and methods of manufacture are discussed. In an embodiment, a method of manufacturing an integrated circuit device includes: forming an optical device layer; forming an optical layer on the optical device layer; after the forming the optical layer, forming a first opening in the optical layer; and embedding a reflective structure in the first opening.

Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.

Abstract: An environment managing and monitoring system and a method using same are provided. The environment managing and monitoring system is configured to assist monitors to obtain real-time information of the monitoring field and control device in the monitoring field. The environmental managing and monitoring system includes at least one sub-system and a host system. The host system is configured to output a region of interest condition and a monitoring condition to the sub-system, wherein the sub-system is configured to generate monitoring results according to the monitoring conditions, and selects an image range from the captured wide-angle dynamic real-time images according to the region of interest condition.

Abstract: Provided is a nanoparticle or a pharmaceutical composition including the same for treating or remitting a neovascularization or an angiogenesis in eye segments, and the nanoparticle includes a hyaluronic acid and a therapeutic peptide.

Abstract: A display device comprises a cover and a display module. The cover includes a bottom plate and at least one cover limit element. The cover limit element projects inwardly from an inner surface of the bottom of the cover. A space is formed between the bottom plate and the cover limit element. The display module includes a frame with at least one frame limit element disposed at an end of the frame and projecting at a position between the cover limit element and the bottom plate. The frame limit element is configured to be disposed in the space and between the cover limit element and the bottom plate to retain the display module with the cover.

Abstract: A display device comprises a cover and a display module. The cover includes a bottom plate and at least one cover limit element. The cover limit element projects inwardly from an inner surface of the bottom of the cover. A space is formed between the bottom plate and the cover limit element. The display module includes a frame with at least one frame limit element disposed at an end of the frame and projecting at a position between the cover limit element and the bottom plate. The frame limit element is configured to be disposed in the space and between the cover limit element and the bottom plate to retain the display module with the cover.

Abstract: A system and method for automatic SPC chart generation including a storage device and a data acquisition module. The storage device stores a chamber management tree, a recipe window management tree, a parameter configuration table and multiple chart profile records. The data acquisition module, which resides in a memory, acquires multiple process events and parameter values corresponding to the process events and a process parameter, selects a relevant statistical algorithm, calculates a statistical value by applying the statistical algorithm to the parameter values, creates a new chart profile record and a parameter statistics record therein if the chart profile record is absent, and stores the statistical values and measured time in the parameter statistics record.

Abstract: A system and method for automatic SPC chart generation including a storage device and a data acquisition module. The storage device stores a chamber management tree, a recipe window management tree, a parameter configuration table and multiple chart profile records. The data acquisition module, which resides in a memory, acquires multiple process events and parameter values corresponding to the process events and a process parameter, selects a relevant statistical algorithm, calculates a statistical value by applying the statistical algorithm to the parameter values, creates a new chart profile record and a parameter statistics record therein if the chart profile record is absent, and stores the statistical values and measured time in the parameter statistics record.

Abstract: An apparatus and method for detecting mispositioned wafers attributable to transfer shift of the wafer are disclosed. A calibration wafer has a target region comprising a pattern of optically distinguishable features from which is determined the position of the calibration wafer within the chamber subsequent to its transfer therein. Preferably, the features comprise a pattern of colors that can be detected by spectroscopy. A preferred form and manner of providing such color features is by way of dielectric thin film filters.

Abstract: An apparatus and method for detecting in chamber wafer position and process status are disclosed. A chamber includes a processing pedestal and plurality of lift pins. Each lift pin has an associated load cell for measuring the load exerted by the wafer on the lift pins. Mispositioned wafers or broken wafers will result in load measurements outside of expected ranges. Position of the wafer may be determined from the load distribution sensed on the lift pins.

Abstract: An apparatus and method for detecting in chamber wafer position and process status are disclosed. A chamber includes a processing pedestal and plurality of lift pins. Each lift pin has an associated load cell for measuring the load exerted by the wafer on the lift pins. Mispositioned wafers or broken wafers will result in load measurements outside of expected ranges. Position of the wafer may be determined from the load distribution sensed on the lift pins.

Abstract: An apparatus and method for detecting mispositioned wafers attributable to transfer shift of the wafer are disclosed. A calibration wafer has a target region comprising a pattern of optically distinguishable features from which is determined the position of the calibration wafer within the chamber subsequent to its transfer therein. Preferably, the features comprise a pattern of colors that can be detected by spectroscopy. A preferred form and manner of providing such color features is by way of dielectric thin film filters.