Abstract: A semiconductor device structure and methods of forming the same are described. The structure includes a first semiconductor material disposed over a substrate and a dielectric layer disposed on the first semiconductor material. The dielectric layer includes a dopant. The structure further includes a second semiconductor material disposed on the dielectric layer, a first semiconductor layer in contact with the second semiconductor material, and a first dielectric spacer in contact with the first semiconductor layer, wherein the first dielectric spacer includes the dopant.

Abstract: A method includes forming first nanostructures over a substrate, then forming second nanostructures over the plurality of first nanostructures. A first source/drain region is epitaxially grown adjacent the first nanostructures, and a second source/drain region is epitaxially grown over the first source/drain region and adjacent the second nanostructures. An implantation process is performed to implant impurities into the second source/drain region, wherein the implantation process forms an amorphous region within the second source/drain region. At least one rapid thermal process is performed on the second source/drain region, wherein performing each rapid thermal process recrystallizes a portion of the amorphous region.

Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

Abstract: A method includes depositing a multi-layer stack on a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a dummy gate on the multi-layer stack; forming a first spacer on a sidewall of the dummy gate; performing a first implantation process to form a first doped region, the first implantation process having a first implant energy and a first implant dose; performing a second implantation process to form a second doped region, where the first doped region and the second doped region are in a portion of the channel layers uncovered by the first spacer and the dummy gate, the second implantation process having a second implant energy and a second implant dose, where the second implant energy is greater than the first implant energy, and where the first implant dose is different from the second implant dose.

Abstract: A system and method for creating, managing, and displaying 3D digital collectibles comprising a virtual, three dimensional, n-sided structure including a digital media file or set of digital media files representing an event rendered on a representation of at least a first surface thereof, and data relating to the event rendered on at least a second surface thereof and other content on one or more other surfaces, where the digital media file may be video clip of the event that can be played automatically via a media player associated with the display.

Abstract: A system and method for creating, managing, and displaying packs of 3D digital collectibles comprising a virtual, three dimensional, n-sided structure including a digital media file or set of digital media files representing an event rendered on a representation of a first surface thereof, and data relating to the event rendered on at least a second surface thereof, where the digital media file may be a video clip of the event that can be played automatically via a media player associated with the display. The system may provide a graphical user interface that displays a set of user tools to interact with the packs of 3D digital collectibles and to display the 3D digital collectibles of the packs and serially play the digital media files of the 3D digital collectibles.

Abstract: A system and method for creating, managing, and displaying 3D digital collectibles comprising a virtual, three dimensional, n-sided structure including a digital media file or set of digital media files representing an event rendered on a representation of at least a first surface thereof, and data relating to the event rendered on at least a second surface thereof and other content on one or more other surfaces, where the digital media file may be video clip of the event that can be played automatically via a media player associated with the display.

Abstract: A system and method for creating, managing, and displaying 3D digital collectibles comprising a virtual, three dimensional, n-sided structure including a digital media file or set of digital media files representing an event rendered on a representation of at least a first surface thereof, and data relating to the event rendered on at least a second surface thereof and other content on one or more other surfaces, where the digital media file may be video clip of the event that can be played automatically via a media player associated with the display.

Abstract: A system and method for creating, managing, and displaying 3D digital collectibles comprising a virtual, three dimensional, n-sided structure including a digital media file or set of digital media files representing an event rendered on a representation of at least a first surface thereof, and data relating to the event rendered on at least a second surface thereof and other content on one or more other surfaces, where the digital media file may be video clip of the event that can be played automatically via a media player associated with the display.

Abstract: This invention relates to a method for forming a gate dielectric layer, and, more particularly, to a method for treating a base oxide layer by using a remote plasma nitridation procedure and a thermal annealing treatment in turn to form the gate dielectric layer. The first step of the present invention is to form a base oxide layer on a substrate of a wafer. The base oxide layer can be formed using any kind of method. Then nitrogen ions are introduced into the base oxide layer using the remote plasma nitridation procedure to form a remote plasma nitrided oxide layer. Finally, the wafer is placed in a reaction chamber which comprises oxygen (O2) or nitric monoxide (NO) to treat the remote plasma nitrided oxide layer using the thermal annealing procedure and the gate dielectric layer of the present invention is formed.