Abstract: A management method for a non-volatile memory comprises the steps of providing the non-volatile memory with at least one block having a plurality of pages to store user data and parity data; dividing at least one of the pages into a plurality of partitions each including the user data and parity data; determining codeword length of each of the partitions, the codeword length comprising message length with sufficient storage to store the user data and parity length storing the parity data; and storing extra parity data in the partition with the codeword length. When storing extra parity data in the codeword length, the parity length is increased and the message length is decreased.

Abstract: A built-in self-test system applied to NAND flash memory comprises a built-in self-test circuit, a built-in redundancy-analysis circuit, a content addressable memory, a spare memory, a page-mode processor and an address generator. The built-in self-test circuit is configured to test for defective data in a NAND flash memory. The built-in redundancy-analysis circuit is connected to the built-in self-test circuit. The content addressable memory is connected to the built-in redundancy-analysis circuit for storing the address of the defective data. The spare memory is electrically connected to the content addressable memory. The page-mode processor is configured to generate a page address signal and a compensation signal according to an address signal of the NAND flash memory. The address generator is configured to generate a current address signal according to the page address signal and compensation signal to the content addressable memory.

Abstract: A management method for a non-volatile memory comprises the steps of providing the non-volatile memory with at least one block having a plurality of pages to store user data and parity data; dividing at least one of the pages into a plurality of partitions each including the user data and parity data; determining codeword length of each of the partitions, the codeword length comprising message length with sufficient storage to store the user data and parity length storing the parity data; and storing extra parity data in the partition with the codeword length. When storing extra parity data in the codeword length, the parity length is increased and the message length is decreased.

Abstract: A built-in self-test system applied to NAND flash memory comprises a built-in self-test circuit, a built-in redundancy-analysis circuit, a content addressable memory, a spare memory, a page-mode processor and an address generator. The built-in self-test circuit is configured to test for defective data in a NAND flash memory. The built-in redundancy-analysis circuit is connected to the built-in self-test circuit. The content addressable memory is connected to the built-in redundancy-analysis circuit for storing the address of the defective data. The spare memory is electrically connected to the content addressable memory. The page-mode processor is configured to generate a page address signal and a compensation signal according to an address signal of the NAND flash memory. The address generator is configured to generate a current address signal according to the page address signal and compensation signal to the content addressable memory.