Patents by Inventor Yu-Ying Lee

Yu-Ying Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10734337
    Abstract: A micro-electromechanical systems (MEMS) package structure includes: (1) a circuit layer; (2) a MEMS die with an active surface, wherein the active surface faces the circuit layer; (3) a conductive pillar adjacent to the MEMS die; and (4) a package body encapsulating the MEMS die and the conductive pillar, and exposing a top surface of the conductive pillar.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: August 4, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuang-Hsiung Chen, Yu-Hsuan Tsai, Yu-Ying Lee, Sheng-Ming Wang, Wun-Jheng Syu
  • Publication number: 20200227414
    Abstract: A semiconductor structure includes a memory array. The memory array has a plurality of memory units. The memory units include a first memory unit and a second memory unit. The first memory unit has a first resistance. The second memory unit has a second resistance. Both of the first resistance and the second resistance are in a range of 105? to 109?, and the second resistance is larger than the first resistance.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 16, 2020
    Inventors: Chao-Hung WANG, Yu-Hsuan LIN, Dai-Ying LEE
  • Publication number: 20200227534
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.
    Type: Application
    Filed: April 1, 2020
    Publication date: July 16, 2020
    Inventors: Kuo-Cheng CHIANG, Chen-Feng HSU, Chao-Ching CHENG, Tzu-Chiang CHEN, Tung Ying LEE, Wei-Sheng YUN, Yu-Lin YANG
  • Patent number: 10714597
    Abstract: An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Tung Ying Lee
  • Patent number: 10714592
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Chen-Feng Hsu, Tzu-Chiang Chen, Tung Ying Lee, Wei-Sheng Yun, Yu-Lin Yang
  • Patent number: 10693009
    Abstract: A semiconductor device includes a fin feature in a substrate, a stack of semiconductor layers over the fin feature. Each of the semiconductor layers does not contact each other. The device also includes a semiconductor oxide layer interposed between the fin feature and the stack of the semiconductor layers. A surface of the semiconductor oxide layer contacts the fin feature and an opposite surface of the semiconductor oxide layer contacts a bottom layer of the stack of semiconductor layers. The device also includes a conductive material layer encircling each of the semiconductor layers and filling in spaces between each of two semiconductor layers.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien Huang, Tung Ying Lee, Chun-Hsiang Fan
  • Publication number: 20200188465
    Abstract: The present invention provides a new method for decreasing level of a proinflammatory cytokine in a subject, which is further able to treating cytokine release syndrome caused by CAR T-cell therapy or a disorder mediated by an overproduction of a proinflammatory cytokine. The method comprises administering to the subject in need thereof a therapeutically effective amount of a pharmaceutical composition which is comprising at least one selected from the group consisting of Phenothiazine derivatives, Graptopetalum paraguayense extract, Rhodiola rosea extract and Histone Deacetylase (HDAC) inhibitors.
    Type: Application
    Filed: December 11, 2019
    Publication date: June 18, 2020
    Inventors: Yu-Chen Tsai, Chi-Ying Huang, Ming-Hsi Chuang, Po-Cheng Lin, Chia-Hsin Lee
  • Patent number: 10672667
    Abstract: Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching Cheng, Tzu-Chiang Chen, Chen-Feng Hsu, Yu-Lin Yang, Tung Ying Lee, Chih Chieh Yeh
  • Patent number: 10665765
    Abstract: A semiconductor device package includes a carrier, a semiconductor device, a lid, a conductive post, a first patterned conductive layer, a conductive element disposed between the first conductive post and the first patterned conductive layer, and an adhesive layer disposed between the lid and the carrier. The conductive post is electrically connected to the first patterned conductive layer. The semiconductor device is electrically connected to the first patterned conductive layer. The lid is disposed on the carrier, and the lid includes a second patterned conductive layer electrically connected to the first conductive post.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: May 26, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Mei-Yi Wu, Lu-Ming Lai, Yu-Ying Lee, Yung-Yi Chang
  • Publication number: 20200152870
    Abstract: A method of forming a phase change random access memory (PCRAM) device includes forming a phase change element over a bottom electrode and a top electrode over the phase change element, forming a protection layer around the phase change element, and forming a nitrogen-containing sidewall spacer layer around the protection layer after forming the protection layer.
    Type: Application
    Filed: July 11, 2019
    Publication date: May 14, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chao LIN, Yuan-Tien TU, Shao-Ming YU, Tung-Ying LEE
  • Patent number: 10636891
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: April 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lin Yang, Tung Ying Lee, Shao-Ming Yu, Chao-Ching Cheng, Tzu-Chiang Chen, Chao-Hsien Huang
  • Publication number: 20200083110
    Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Publication number: 20200058859
    Abstract: A resistive memory device includes a first electrode, a resistance switching layer and a second electrode. The resistance switching layer is disposed on the first electrode and includes a ternary transition metal oxide. The second electrode is disposed on the resistance switching layer.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Inventors: Chao-Hung WANG, Dai-Ying LEE, Kuang-Hao CHIANG, Yu-Hsuan LIN, Tsung-Ming CHEN
  • Publication number: 20200052091
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.
    Type: Application
    Filed: October 18, 2019
    Publication date: February 13, 2020
    Inventors: Chao-Ching CHENG, Chen-Feng HSU, Tzu-Chiang CHEN, Tung Ying LEE, Wei-Sheng YUN, Yu-Lin YANG
  • Publication number: 20200052086
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers.
    Type: Application
    Filed: October 18, 2019
    Publication date: February 13, 2020
    Inventors: Yu-Lin YANG, Tung Ying LEE, Shao-Ming YU, Chao-Ching CHENG, Tzu-Chiang CHEN, Chao-Hsien HUANG
  • Publication number: 20200043803
    Abstract: Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.
    Type: Application
    Filed: October 11, 2019
    Publication date: February 6, 2020
    Inventors: Chao-Ching Cheng, Tzu-Chiang Chen, Chen-Feng Hsu, Yu-Lin Yang, Tung Ying Lee, Chih Chieh Yeh
  • Patent number: 10515884
    Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure, a dielectric structure and a metal bump. The conductive structure has a first conductive surface and a second conductive surface. The dielectric structure has a first dielectric surface and a second dielectric surface. The first conductive surface does not protrude from the first dielectric surface. The second conductive surface is recessed from the second dielectric surface. The metal bump is disposed in a dielectric opening of the dielectric structure, and is physically and electrically connected to the second conductive surface. The metal bump has a concave surface.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: December 24, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, Yu-Ying Lee, Li-Chuan Tsai, Chih-Cheng Lee
  • Publication number: 20190383990
    Abstract: A quantum dot composite material and a manufacturing method and an application thereof are provided. The quantum dot composite material includes an all-inorganic perovskite quantum dot and a modification protection on a surface of the all-inorganic perovskite quantum dot. The all-inorganic perovskite quantum dot has a chemical formula of CsPb(ClaBr1-a-bIb)3, wherein 0?a?1, 0?b?1.
    Type: Application
    Filed: August 23, 2019
    Publication date: December 19, 2019
    Inventors: Hung-Chia Wang, Xue-Jie Zhang, Shin-Ying Lin, An-Cih Tang, Ru-Shi Liu, Tzong-Liang Tsai, Yu-Chun Lee, Ching-Yi Chen, Hung-Chun Tong
  • Patent number: 10504792
    Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Patent number: 10490744
    Abstract: A contact hole structure includes a substrate, an interlayer dielectric (ILD), a conductive layer and an insulating capping layer. The ILD is disposed on the substrate and has a first opening. The conductive layer is disposed in the ILD and aligns the first opening. The insulating capping layer has a spacer disposed on a first sidewall of the first opening, wherein the spacer contacts to the conductive layer and defines a second opening in the first opening, so as to expose a portion of the conductive layer.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: November 26, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Dai-Ying Lee, Po-Hao Tseng, Feng-Min Lee, Yu-Yu Lin, Kai-Chieh Hsu