Patents by Inventor Yu-Ying Lee
Yu-Ying Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136183Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Inventors: Yu-Shih Wang, Hong-Jie Yang, Chia-Ying Lee, Po-Nan Yeh, U-Ting Chiu, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
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Publication number: 20240122163Abstract: The present invention demonstrated a Cre-loxP based cofilin-1 transgenic animal model to address the pathophysiological role of over-expressed cofilin-1 on systemic development.Type: ApplicationFiled: February 6, 2023Publication date: April 18, 2024Inventors: Yi-Jang LEE, Yu-Chuan LIN, Min-Ying LIN, Bing-Ze LIN, Chia-Yun KANG
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Publication number: 20240120317Abstract: A fan-out semiconductor device includes stacked semiconductor dies having die bond pads arranged in columns exposed at a sidewall of the stacked semiconductor dies. The stacked dies are encapsulated in a photo imageable dielectric (PID) material, which is developed to form through-hole cavities that expose the columns of bond pads of each die at the sidewall. The through-hole cavities are plated or filled with an electrical conductor to form conductive through-holes coupling die bond pads within the columns to each other.Type: ApplicationFiled: July 13, 2023Publication date: April 11, 2024Applicant: Western Digital Technologies, Inc.Inventors: Cheng-Hsiung Yang, Chien Te Chen, Cong Zhang, Ching-Chuan Hsieh, Yu-Ying Tan, Juan Zhou, Ai-wen Wang, Yih-Fran Lee, Yu-Wen Huang
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Patent number: 11935958Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first stacked nanostructure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure includes a second gate structure formed over the second stacked nanostructure, and the second gate structure includes a second portion of the gate dielectric layer and a second portion of the filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, wherein the first isolation layer has an extending portion which is formed in a recess between the gate dielectric layer and the filling layer.Type: GrantFiled: March 27, 2023Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chao Lin, Wei-Sheng Yun, Tung-Ying Lee
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Publication number: 20240090354Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, a top electrode, and a storage element layer. The storage element layer is disposed between the bottom and top electrodes. An extending direction of a sidewall of the storage element layer is different from an extending direction of a sidewall of the top electrode. A semiconductor device having the memory cell is also provided.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chao Lin, Tung-Ying Lee
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Publication number: 20240090238Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.Type: ApplicationFiled: November 27, 2023Publication date: March 14, 2024Inventors: Feng-Min LEE, Erh-Kun LAI, Dai-Ying LEE, Yu-Hsuan LIN, Po-Hao TSENG, Ming-Hsiu LEE
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Patent number: 11925127Abstract: A method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a phase-change material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is level with or below the top surface of the dielectric layer; and forming a top electrode on the PCM layer.Type: GrantFiled: July 15, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tung Ying Lee, Yu Chao Lin, Shao-Ming Yu
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Publication number: 20240071821Abstract: A semiconductor element and a method for manufacturing the same are provided. The semiconductor element includes a plug and a via on the plug and electrically connected to the plug. The plug includes a tungsten plug and a conductive layer on the tungsten plug. The tungsten plug and the conductive layer include different materials. The tungsten plug has a first width in a lateral direction. The conductive layer has a second width in the lateral direction. The second width is greater than or equal to the first width. The conductive layer is between the via and the tungsten plug.Type: ApplicationFiled: August 23, 2022Publication date: February 29, 2024Inventors: Dai-Ying LEE, Yu-Chao HUANG
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Patent number: 11862550Abstract: An electronic package structure and a method of manufacturing an electronic package structure are provided. The electronic package structure includes a substrate, a conductive element, and a support structure. The substrate has a bottom surface and a lateral surface angled with the bottom surface. The conductive element is on the lateral surface of the substrate. The support structure is on the bottom surface of the substrate and configured to space the bottom surface from an external carrier. A lateral surface of the support structure is spaced apart from the lateral surface of the substrate by a first distance.Type: GrantFiled: September 30, 2021Date of Patent: January 2, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Yu-Ying Lee
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Patent number: 11784296Abstract: A semiconductor device package includes a carrier, a semiconductor device, a lid, a conductive post, a first patterned conductive layer, a conductive element disposed between the first conductive post and the first patterned conductive layer, and an adhesive layer disposed between the lid and the carrier. The conductive post is electrically connected to the first patterned conductive layer. The semiconductor device is electrically connected to the first patterned conductive layer. The lid is disposed on the carrier, and the lid includes a second patterned conductive layer electrically connected to the first conductive post.Type: GrantFiled: December 28, 2021Date of Patent: October 10, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Mei-Yi Wu, Lu-Ming Lai, Yu-Ying Lee, Yung-Yi Chang
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Publication number: 20230317589Abstract: A package structure includes a first die, a second die, an encapsulant and at least one electrical contact. The first die has an active surface. The second die is disposed on the first die, and has an active surface and a backside surface opposite to the active surface. The active surface of the second die is closer to the active surface of the first die than the backside surface of the second die is. The encapsulant encapsulates the first die and the second die, and has a top surface far away from the active surface of the first die. The electrical contact is exposed from the top surface of the encapsulant and is configured for connecting at least one conductive wire.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Yu-Ying Lee
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Publication number: 20230096703Abstract: An electronic package structure and a method of manufacturing an electronic package structure are provided. The electronic package structure includes a substrate, a conductive element, and a support structure. The substrate has a bottom surface and a lateral surface angled with the bottom surface. The conductive element is on the lateral surface of the substrate. The support structure is on the bottom surface of the substrate and configured to space the bottom surface from an external carrier. A lateral surface of the support structure is spaced apart from the lateral surface of the substrate by a first distance.Type: ApplicationFiled: September 30, 2021Publication date: March 30, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Yu-Ying LEE
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Publication number: 20230030133Abstract: A semiconductor device package includes a carrier, a first conductive post and a first adhesive layer. The first conductive post is disposed on the carrier. The first conductive post includes a lower surface facing the carrier, an upper surface opposite to the lower surface and a lateral surface extended between the upper surface and the lower surface. The first adhesive layer surrounds a portion of the lateral surface of the first conductive post. The first adhesive layer comprises conductive particles and an adhesive. The first conductive post has a height measured from the upper surface to the lower surface and a width. The height is greater than the width.Type: ApplicationFiled: October 11, 2022Publication date: February 2, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Yu-Ying LEE
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Patent number: 11569179Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The package structure includes an outer lead portion, an inner lead portion, an encapsulant, and a first conductive layer. The outer lead portion has a first surface and a second surface opposite to the first surface. The inner lead portion is connected to the outer lead portion. The inner lead portion has a first surface and a second surface opposite to the first surface. The encapsulant covers the first surface of the outer lead portion and the first surface of the inner lead portion. The second surface of the outer lead portion and the second surface of the inner lead portion are substantially coplanar and are recessed from a surface of the encapsulant. The first conductive layer is disposed on the second surface of the outer lead portion.Type: GrantFiled: November 19, 2020Date of Patent: January 31, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Yu-Ying Lee
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Patent number: 11469165Abstract: A semiconductor device package includes a carrier, a first conductive post and a first adhesive layer. The first conductive post is disposed on the carrier. The first conductive post includes a lower surface facing the carrier, an upper surface opposite to the lower surface and a lateral surface extended between the upper surface and the lower surface. The first adhesive layer surrounds a portion of the lateral surface of the first conductive post. The first adhesive layer comprises conductive particles and an adhesive. The first conductive post has a height measured from the upper surface to the lower surface and a width. The height is greater than the width.Type: GrantFiled: July 17, 2020Date of Patent: October 11, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Yu-Ying Lee
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Publication number: 20220157742Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The package structure includes an outer lead portion, an inner lead portion, an encapsulant, and a first conductive layer. The outer lead portion has a first surface and a second surface opposite to the first surface. The inner lead portion is connected to the outer lead portion. The inner lead portion has a first surface and a second surface opposite to the first surface. The encapsulant covers the first surface of the outer lead portion and the first surface of the inner lead portion. The second surface of the outer lead portion and the second surface of the inner lead portion are substantially coplanar and are recessed from a surface of the encapsulant. The first conductive layer is disposed on the second surface of the outer lead portion.Type: ApplicationFiled: November 19, 2020Publication date: May 19, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Yu-Ying LEE
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Publication number: 20220123192Abstract: A semiconductor device package includes a carrier, a semiconductor device, a lid, a conductive post, a first patterned conductive layer, a conductive element disposed between the first conductive post and the first patterned conductive layer, and an adhesive layer disposed between the lid and the carrier. The conductive post is electrically connected to the first patterned conductive layer. The semiconductor device is electrically connected to the first patterned conductive layer. The lid is disposed on the carrier, and the lid includes a second patterned conductive layer electrically connected to the first conductive post.Type: ApplicationFiled: December 28, 2021Publication date: April 21, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Mei-Yi Wu, Lu-Ming Lai, Yu-Ying Lee, Yung-Yi Chang
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Patent number: 11211536Abstract: A semiconductor device package includes a carrier, a semiconductor device, a lid, a conductive post, a first patterned conductive layer, a conductive element disposed between the first conductive post and the first patterned conductive layer, and an adhesive layer disposed between the lid and the carrier. The conductive post is electrically connected to the first patterned conductive layer. The semiconductor device is electrically connected to the first patterned conductive layer. The lid is disposed on the carrier, and the lid includes a second patterned conductive layer electrically connected to the first conductive post.Type: GrantFiled: April 29, 2020Date of Patent: December 28, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Mei-Yi Wu, Lu-Ming Lai, Yu-Ying Lee, Yung-Yi Chang
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Patent number: 10879159Abstract: A substrate, a semiconductor package thereof and a process of making the same are provided. The substrate comprises an upper circuit layer and a lower circuit layer, the upper circuit layer comprising at least one trace and at least one pad and the lower circuit layer comprising at least one trace and at least one pad, wherein the trace of the upper circuit layer and the trace of the lower circuit layer are not aligned.Type: GrantFiled: May 5, 2015Date of Patent: December 29, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tien-Szu Chen, Sheng-Ming Wang, Kuang-Hsiung Chen, Yu-Ying Lee
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Publication number: 20200350239Abstract: A semiconductor device package includes a carrier, a first conductive post and a first adhesive layer. The first conductive post is disposed on the carrier. The first conductive post includes a lower surface facing the carrier, an upper surface opposite to the lower surface and a lateral surface extended between the upper surface and the lower surface. The first adhesive layer surrounds a portion of the lateral surface of the first conductive post. The first adhesive layer comprises conductive particles and an adhesive. The first conductive post has a height measured from the upper surface to the lower surface and a width. The height is greater than the width.Type: ApplicationFiled: July 17, 2020Publication date: November 5, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Yu-Ying LEE