Abstract: The present invention relates to a method of debugging a targeted area or the whole network-on-chip (NOC) (101), whereby said targeted area or the whole NOC is triggered to enter into a freeze state before capturing of the state of the targeted area or the whole NOC (101) and unloading of the debug information, before finally said targeted area or the whole NOC is triggered to enter into an unfreeze state to allow forward progress to resume, using existing buffer storage, thus allowing user to debug and identify the source of issue without requiring a significant amount of extra storage.

Abstract: A memory controller system (and method of pre-scheduling memory transaction) for a storage device comprising a linked-list controller; a plurality of command buffers to store read commands or write commands, and an arbiter to issue command. Each command buffer containing variables set by the linked-list controller. The linked-list controller is configured to execute commands in sequence independent of logical command buffer sequence. The command buffer is configured to support read commands with maximum number of write commands. The linked-list controller is configured to merge multiple write commands that are going to the same address and snarfs read commands from write commands if both commands are going to the same address and the read commands that are snarfed are loaded into a separate command buffer. The variables contained in each of the command buffer indicates status and dependency of the command buffer to create a link forming a command sequence.

Abstract: An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.

Abstract: Described herein are memory controllers for integrated circuits that implement network-on-chip (NoC) to provide access to memory to couple processing cores of the integrated circuit to a memory device. The NoC may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.

Abstract: A memory controller system (and method of pre-scheduling memory transaction) for a storage device comprising a linked-list controller; a plurality of command buffers to store read commands or write commands, and an arbiter to issue command. Each command buffer containing variables set by the linked-list controller. The linked-list controller is configured to execute commands in sequence independent of logical command buffer sequence. The command buffer is configured to support read commands with maximum number of write commands. The linked-list controller is configured to merge multiple write commands that are going to the same address and snarfs read commands from write commands if both commands are going to the same address and the read commands that are snarfed are loaded into a separate command buffer. The variables contained in each of the command buffer indicates status and dependency of the command buffer to create a link forming a command sequence.

Abstract: A memory controller system comprising a scheduling module, a data buffer module, a global order buffer module and a linked-list controlling module. The linked-list controlling module is configured to receive and process a first command comprising a write command or a read command. The linked-list controlling module constructs at least one linked-list head based on scheduling dependencies and determines whether the first command is dependency-hit by comparing the first command with the existing commands buffered in the global order buffer module. If the first command is dependency-hit, the linked-list controlling module is configured to trigger a write merging process or a read snarfing process.

Abstract: Described herein are memory controllers for integrated circuits that implement network-on-chip (NoC) to provide access to memory to couple processing cores of the integrated circuit to a memory device. The NoC may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.

Abstract: The present invention relates a network-on-chip (NoC) system for optimizing data transfer, the system comprising a plurality of nodes including a source node and a destination node; characterized by a plurality of routers attached to the plurality of nodes that route a plurality of data packets from the source node to the destination node; wherein each of the plurality of packets is tagged with a routing information (RINFO), each node is assigned with a node unique identifier (ID) and each router is assigned with a router unique identifier (RID) for each horizontal and vertical routing direction for 2D and 3D interconnect topologies; wherein each of the router comprising at least a pair of ingress port and egress port, a route decoder and an arbiter to support a synchronous, an asynchronous and a source-synchronous operations. The present invention also relates to a method of optimizing data transfer using the NoC system.

Abstract: A device and method of clock synchronization for external memory interface. The device, and method, generating a clock output from a phase lock loop block via a sub-module clocking component; multiplexing the clock output through a global clock into different clock domains; clocking the data and an address or a command path by each clock domain; clocking the phase compensation FIFO by clock domain and clock phase alignment clock; generating the pointer for the phase compensation FIFO from central pointer generator block; and synchronizing the pointer of the adjacent intellectual property module with a parent intellectual property module.

Abstract: A memory controller for improving data integrity and providing data security. The memory controller including a transmit data path to transmit write data to a memory device, the transmit data path comprising a scrambling component, wherein the scrambling component includes a scrambling logic and an exclusive OR logic, wherein the write data is divided into a first portion and a second portion, wherein input of the scrambling logic comprises the first portion of the write data and an address associated with the write data to generate a pseudo-random output, and wherein input of the exclusive OR logic comprises the second portion of the write data, the pseudo-random output and a fixed seed corresponding to the first portion of the write data to generate a scrambled data.

Abstract: A device and method of clock synchronization for external memory interface. The device, and method, generating a clock output from a phase lock loop block via a sub-module clocking component; multiplexing the clock output through a global clock into different clock domains; clocking the data and an address or a command path by each clock domain; clocking the phase compensation FIFO by clock domain and clock phase alignment clock; generating the pointer for the phase compensation FIFO from central pointer generator block; and synchronizing the pointer of the adjacent intellectual property module with a parent intellectual property module.

Abstract: A memory controller system comprising a scheduling module; wherein a data buffer module; a global order buffer module; and a linked-list controlling module to receive and process a first command comprising a write command or a read command; wherein the linked-list controlling module constructs at least one linked-list head based on scheduling dependencies and determines whether the first command is dependency-hit by comparing the first command with the existing commands buffered in the global order buffer module; whereby in a case that the first command is dependency-hit, the linked-list controlling module is configured to trigger a write merging process or a read snarfing process.

Abstract: An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.

Abstract: An integrated circuit may include a memory controller circuit for communicating with an off-chip memory device. The memory controller is operable in a read-write major mode that is capable of dynamically adapting to any memory traffic pattern, which results in improved memory scheduling efficiency across different user applications. The memory controller may include at least a write command queue, a read command queue, an arbiter, and a command scheduler. The command scheduler may monitor a write command count, a read command count, a write stall count, and a read stall count to determine whether to dynamically adjust a read burst threshold setting and a write burst threshold setting.

Abstract: An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.

Abstract: A modular Error Correction Code (ECC) scheme in a multi-channel IO link of an integrated circuit device is provided. The integrated circuit device may include core logic circuitry that may be configured after manufacturing. To accommodate the resulting variation, the modular ECC scheme may allow for partitioning a parity check matrix associated with the configuration of the core logic and peripheries coupled to the core logic. The parity check matrix is partitioned into smaller block matrices that is programmable. Multiple ECC modules corresponding to the block matrices are used to provide error detection and correction in the multi-channel IO link. The modular ECC scheme combined with programmable matrices (configurability) enables multi-channel IO link to be flexible to form different IO topologies.

Abstract: An integrated circuit is operable to communicate with an external component. The integrated circuit may include driver circuits for outputting clock signals and associated control signals to the external component in accordance with a predetermined interface protocol. The clock signals may toggle more frequently than the associated control signals. To help mitigate potential transistor aging effects that could negatively impact timing margins for the control signals, the control signals may be periodically toggled even during idle periods as allowed by the predetermined interface protocol to help improve timing margins.

Abstract: An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.

Abstract: An integrated circuit may include a memory controller circuit for communicating with an off-chip memory device. The memory controller is operable in a read-write major mode that is capable of dynamically adapting to any memory traffic pattern, which results in improved memory scheduling efficiency across different user applications. The memory controller may include at least a write command queue, a read command queue, an arbiter, and a command scheduler. The command scheduler may monitor a write command count, a read command count, a write stall count, and a read stall count to determine whether to dynamically adjust a read burst threshold setting and a write burst threshold setting.

Abstract: An integrated circuit is operable to communicate with an external component. The integrated circuit may include driver circuits for outputting clock signals and associated control signals to the external component in accordance with a predetermined interface protocol. The clock signals may toggle more frequently than the associated control signals. To help mitigate potential transistor aging effects that could negatively impact timing margins for the control signals, the control signals may be periodically toggled even during idle periods as allowed by the predetermined interface protocol to help improve timing margins.