Patents by Inventor Yu Ying Ong

Yu Ying Ong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12380056
    Abstract: The present invention relates a network-on-chip (NoC) system for optimizing data transfer, the system comprising a plurality of nodes including a source node and a destination node; characterized by a plurality of routers attached to the plurality of nodes that route a plurality of data packets from the source node to the destination node; wherein each of the plurality of packets is tagged with a routing information (RINFO), each node is assigned with a node unique identifier (ID) and each router is assigned with a router unique identifier (RID) for each horizontal and vertical routing direction for 2D and 3D interconnect topologies; wherein each of the router comprising at least a pair of ingress port and egress port, a route decoder and an arbiter to support a synchronous, an asynchronous and a source-synchronous operations. The present invention also relates to a method of optimizing data transfer using the NoC system.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: August 5, 2025
    Assignee: SKYECHIP SDN BHD
    Inventors: Yu Ying Ong, Chee Hak Teh
  • Publication number: 20250138623
    Abstract: The present invention relates to a system for network-on-chip power management. The system comprising a primary network-on-chip comprises multiple components, each component having a power controller, characterized by a secondary network-on-chip comprises a secondary network-on-chip master node and a plurality of secondary network-on-chip nodes connected thereto, the plurality of secondary network-on-chip nodes associated to the components of the primary network-on-chip for power managing individual and link components of the primary network-on-chip, and a power management unit connected to the secondary network-on-chip master node, configured to polling status registers of the components of the primary network-on-chip for accessing power states of each component, accessing routing information of the components of the primary network-on-chip and sending request to the secondary network-on-chip nodes for powering on or off the associated components of the primary network-chip through the power controller.
    Type: Application
    Filed: December 29, 2023
    Publication date: May 1, 2025
    Applicant: SKYECHIP SDN BHD
    Inventors: Chee Hak TEH, Yu Ying ONG, Soon Chieh LIM, MUHAMAD AIDIL BIN JAZMI, Yeong Tat LIEW, Weng Li LEOW
  • Patent number: 12210633
    Abstract: A memory controller for improving data integrity and providing data security. The memory controller including a transmit data path to transmit write data to a memory device, the transmit data path comprising a scrambling component, wherein the scrambling component includes a scrambling logic and an exclusive OR logic, wherein the write data is divided into a first portion and a second portion, wherein input of the scrambling logic comprises the first portion of the write data and an address associated with the write data to generate a pseudo-random output, and wherein input of the exclusive OR logic comprises the second portion of the write data, the pseudo-random output and a fixed seed corresponding to the first portion of the write data to generate a scrambled data.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: January 28, 2025
    Assignee: SKYECHIP SDN BHD
    Inventors: Yu Ying Ong, Muhamad Aidil Bin Jazmi, Soon Chieh Lim, Chee Hak Teh
  • Patent number: 12199884
    Abstract: A method comprises the steps of receiving input from a user via user interface and selecting a plurality of flits from a plurality of ingress into a plurality of virtual channels followed by selecting the flits from the virtual channels into a plurality of egress based on the input from the user. The selection of the flits into the virtual channels and the egress characterized by the steps of computing default and elevated bandwidths of the virtual channels, computing default and elevated weights of the virtual channels based on the default and elevated bandwidths and generating a weightage lookup table using the default and elevated weights to perform arbitration weightage lookup for the flits with default and elevated priority levels for selecting the flits into the virtual channels and the egress, wherein the flits from the different ingress comprise different default and elevated weight.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: January 14, 2025
    Assignee: SKYECHIP SDN BHD
    Inventors: Yeong Tat Liew, Yu Ying Ong, Soon Chieh Lim, Weng Li Leow, Chee Hak Teh
  • Patent number: 12094551
    Abstract: A modular Error Correction Code (ECC) scheme in a multi-channel IO link of an integrated circuit device is provided. The integrated circuit device may include core logic circuitry that may be configured after manufacturing. To accommodate the resulting variation, the modular ECC scheme may allow for partitioning a parity check matrix associated with the configuration of the core logic and peripheries coupled to the core logic. The parity check matrix is partitioned into smaller block matrices that is programmable. Multiple ECC modules corresponding to the block matrices are used to provide error detection and correction in the multi-channel IO link. The modular ECC scheme combined with programmable matrices (configurability) enables multi-channel IO link to be flexible to form different IO topologies.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: September 17, 2024
    Assignee: Intel Corporation
    Inventors: Hwa Chaw Law, Yu Ying Ong
  • Publication number: 20240296140
    Abstract: Described herein are memory controllers for integrated circuits that implement network-on-chip (NoC) to provide access to memory to couple processing cores of the integrated circuit to a memory device. The NoC may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Inventors: Chee Hak Teh, Yu Ying Ong, George Chong Hean Ooi
  • Publication number: 20240297846
    Abstract: The present invention discloses a computer-implemented method of data transmission for a Network-on-Chip to allow high performance routing through dynamic allocated buffer. The method comprises the steps of transferring command or data in a form of plurality of flits from a source node to a router and further to a destination node, and transmitting the flits from the destination node back to the router, wherein the flits are packetized for transmission according to channel width and transaction width, sequence, and priority routing through physical and virtual channels.
    Type: Application
    Filed: June 14, 2023
    Publication date: September 5, 2024
    Applicant: SKYECHIP SDN BHD
    Inventors: Chee Hak TEH, Yu Ying ONG, Soon Chieh LIM, Weng Li LEOW, Yeong Tat LIEW, Chuen Heong KHUAN, Manobindra GANDHI, Muhamad Aidil Bin JAZMI
  • Patent number: 11995028
    Abstract: Described herein are memory controllers for integrated circuits that implement network-on-chip (NoC) to provide access to memory to couple processing cores of the integrated circuit to a memory device. The NoC may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: May 28, 2024
    Assignee: Intel Corporation
    Inventors: Chee Hak Teh, Yu Ying Ong, George Chong Hean Ooi
  • Publication number: 20240163223
    Abstract: The present invention relates to a method (100) for network-on-chip arbitration. The method (100) comprises the steps of receiving input from a user via user interface and selecting a plurality of flits from a plurality of ingress into a plurality of virtual channels followed by selecting the flits from the virtual channels into a plurality of egress based on the input from the user. The selection of the flits into the virtual channels and the egress characterized by the steps of computing default and elevated bandwidths of the virtual channels, computing default and elevated weights of the virtual channels based on the default and elevated bandwidths and generating a weightage lookup table using the default and elevated weights to perform arbitration weightage lookup for the flits with default and elevated priority levels for selecting the flits into the virtual channels and the egress, wherein the flits from the different ingress comprise different default and elevated weight.
    Type: Application
    Filed: December 13, 2022
    Publication date: May 16, 2024
    Applicant: SKYECHIP SDN BHD
    Inventors: YEONG TAT LIEW, YU YING ONG, SOON CHIEH LIM, WENG LI LEOW, CHEE HAK TEH
  • Publication number: 20240070039
    Abstract: The present invention relates to a method of debugging a targeted area or the whole network-on-chip (NOC) (101), whereby said targeted area or the whole NOC is triggered to enter into a freeze state before capturing of the state of the targeted area or the whole NOC (101) and unloading of the debug information, before finally said targeted area or the whole NOC is triggered to enter into an unfreeze state to allow forward progress to resume, using existing buffer storage, thus allowing user to debug and identify the source of issue without requiring a significant amount of extra storage.
    Type: Application
    Filed: October 7, 2022
    Publication date: February 29, 2024
    Inventors: Yu Ying ONG, Chee Hak TEH, Soon Chieh LIM, Weng Li LEOW, Muhamad Aidil BIN JAZMI, Yeong Tat LIEW
  • Patent number: 11829643
    Abstract: A memory controller system (and method of pre-scheduling memory transaction) for a storage device comprising a linked-list controller; a plurality of command buffers to store read commands or write commands, and an arbiter to issue command. Each command buffer containing variables set by the linked-list controller. The linked-list controller is configured to execute commands in sequence independent of logical command buffer sequence. The command buffer is configured to support read commands with maximum number of write commands. The linked-list controller is configured to merge multiple write commands that are going to the same address and snarfs read commands from write commands if both commands are going to the same address and the read commands that are snarfed are loaded into a separate command buffer. The variables contained in each of the command buffer indicates status and dependency of the command buffer to create a link forming a command sequence.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: November 28, 2023
    Assignee: SKYECHIP SDN BHD
    Inventors: Chee Hak Teh, Yu Ying Ong, Weng Li Leow, Muhamad Aidil Bin Jazmi
  • Patent number: 11658159
    Abstract: An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: May 23, 2023
    Assignee: Intel Corporation
    Inventors: Saravanan Sethuraman, Tonia Morris, Siaw Kang Lai, Yee Choong Lim, Yu Ying Ong
  • Publication number: 20230135934
    Abstract: Described herein are memory controllers for integrated circuits that implement network-on-chip (NoC) to provide access to memory to couple processing cores of the integrated circuit to a memory device. The NoC may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.
    Type: Application
    Filed: December 27, 2022
    Publication date: May 4, 2023
    Inventors: Chee Hak Teh, Yu Ying Ong, George Chong Hean Ooi
  • Publication number: 20230129791
    Abstract: A memory controller system (and method of pre-scheduling memory transaction) for a storage device comprising a linked-list controller; a plurality of command buffers to store read commands or write commands, and an arbiter to issue command. Each command buffer containing variables set by the linked-list controller. The linked-list controller is configured to execute commands in sequence independent of logical command buffer sequence. The command buffer is configured to support read commands with maximum number of write commands. The linked-list controller is configured to merge multiple write commands that are going to the same address and snarfs read commands from write commands if both commands are going to the same address and the read commands that are snarfed are loaded into a separate command buffer. The variables contained in each of the command buffer indicates status and dependency of the command buffer to create a link forming a command sequence.
    Type: Application
    Filed: December 27, 2021
    Publication date: April 27, 2023
    Applicant: SKYECHIP SDN BHD
    Inventors: Chee Hak TEH, Yu Ying ONG, Weng Li LEOW, Muhamad Aidil Bin JAZMI
  • Patent number: 11609709
    Abstract: A memory controller system comprising a scheduling module, a data buffer module, a global order buffer module and a linked-list controlling module. The linked-list controlling module is configured to receive and process a first command comprising a write command or a read command. The linked-list controlling module constructs at least one linked-list head based on scheduling dependencies and determines whether the first command is dependency-hit by comparing the first command with the existing commands buffered in the global order buffer module. If the first command is dependency-hit, the linked-list controlling module is configured to trigger a write merging process or a read snarfing process.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: March 21, 2023
    Assignee: SKYECHIP SDN BHD
    Inventors: Chee Hak Teh, Yu Ying Ong
  • Patent number: 11580054
    Abstract: Described herein are memory controllers for integrated circuits that implement network-on-chip (NoC) to provide access to memory to couple processing cores of the integrated circuit to a memory device. The NoC may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: February 14, 2023
    Assignee: Intel Corporation
    Inventors: Chee Hak Teh, Yu Ying Ong, George Chong Hean Ooi
  • Publication number: 20230040323
    Abstract: The present invention relates a network-on-chip (NoC) system for optimizing data transfer, the system comprising a plurality of nodes including a source node and a destination node; characterized by a plurality of routers attached to the plurality of nodes that route a plurality of data packets from the source node to the destination node; wherein each of the plurality of packets is tagged with a routing information (RINFO), each node is assigned with a node unique identifier (ID) and each router is assigned with a router unique identifier (RID) for each horizontal and vertical routing direction for 2D and 3D interconnect topologies; wherein each of the router comprising at least a pair of ingress port and egress port, a route decoder and an arbiter to support a synchronous, an asynchronous and a source-synchronous operations. The present invention also relates to a method of optimizing data transfer using the NoC system.
    Type: Application
    Filed: October 12, 2022
    Publication date: February 9, 2023
    Inventors: YU YING ONG, CHEE HAK TEH
  • Patent number: 11575383
    Abstract: A device and method of clock synchronization for external memory interface. The device, and method, generating a clock output from a phase lock loop block via a sub-module clocking component; multiplexing the clock output through a global clock into different clock domains; clocking the data and an address or a command path by each clock domain; clocking the phase compensation FIFO by clock domain and clock phase alignment clock; generating the pointer for the phase compensation FIFO from central pointer generator block; and synchronizing the pointer of the adjacent intellectual property module with a parent intellectual property module.
    Type: Grant
    Filed: February 6, 2021
    Date of Patent: February 7, 2023
    Assignee: SKYECHIP SDN BHD
    Inventors: Chee Hak Teh, Yu Ying Ong, Wong Ging Yeon Mark, Tat Hin Tan, Soong Khim Chew
  • Publication number: 20220253536
    Abstract: A memory controller for improving data integrity and providing data security. The memory controller including a transmit data path to transmit write data to a memory device, the transmit data path comprising a scrambling component, wherein the scrambling component includes a scrambling logic and an exclusive OR logic, wherein the write data is divided into a first portion and a second portion, wherein input of the scrambling logic comprises the first portion of the write data and an address associated with the write data to generate a pseudo-random output, and wherein input of the exclusive OR logic comprises the second portion of the write data, the pseudo-random output and a fixed seed corresponding to the first portion of the write data to generate a scrambled data.
    Type: Application
    Filed: February 18, 2021
    Publication date: August 11, 2022
    Applicant: SKYECHIP SDN BHD
    Inventors: YU YING ONG, MUHAMAD AIDIL BIN JAZMI, SOON CHIEH LIM, CHEE HAK TEH
  • Publication number: 20220200610
    Abstract: A device and method of clock synchronization for external memory interface. The device, and method, generating a clock output from a phase lock loop block via a sub-module clocking component; multiplexing the clock output through a global clock into different clock domains; clocking the data and an address or a command path by each clock domain; clocking the phase compensation FIFO by clock domain and clock phase alignment clock; generating the pointer for the phase compensation FIFO from central pointer generator block; and synchronizing the pointer of the adjacent intellectual property module with a parent intellectual property module.
    Type: Application
    Filed: February 6, 2021
    Publication date: June 23, 2022
    Applicant: SKYECHIP SDN BHD
    Inventors: CHEE HAK TEH, YU YING ONG, Wong Ging Yeon MARK, Tat Hin TAN, Soong Khim CHEW