Patents by Inventor Yu YING

Yu YING has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Substrate having a conductive structure within photo-sensitive resin
    Patent number: 10515884
    Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure, a dielectric structure and a metal bump. The conductive structure has a first conductive surface and a second conductive surface. The dielectric structure has a first dielectric surface and a second dielectric surface. The first conductive surface does not protrude from the first dielectric surface. The second conductive surface is recessed from the second dielectric surface. The metal bump is disposed in a dielectric opening of the dielectric structure, and is physically and electrically connected to the second conductive surface. The metal bump has a concave surface.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: December 24, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, Yu-Ying Lee, Li-Chuan Tsai, Chih-Cheng Lee
  • GLASS SUBSTRATE PROCESSING METHODS
    Publication number: 20190382307
    Abstract: Described is a method of processing an antimicrobial glass substrate. More particularly, described is a method of removing one or more of silver nitrate or silver oxide on the surface of an antimicrobial glass substrate. Also described is a method of manufacturing a glass substrate that is substantially free of yellow discoloration.
    Type: Application
    Filed: June 12, 2019
    Publication date: December 19, 2019
    Inventors: Tien San Chi, Chih Yuan Lu, Cheng-Da Tsai, Yu Ying Tsai, Shan Zhu
  • Polysilicon Design for Replacement Gate Technology
    Publication number: 20190386116
    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.
    Type: Application
    Filed: August 30, 2019
    Publication date: December 19, 2019
    Inventors: Harry-Hak-Lay Chuang, Kong-Beng Thei, Sheng-Chen Chung, Chiung-Han Yeh, Lee-Wee Teo, Yu-Ying Hsu, Bao-Ru Young
  • Embedded trace substrate structure and semiconductor package structure including the same
    Patent number: 10483196
    Abstract: A substrate structure includes a carrier, a first metal layer, a circuit layer and a dielectric layer. The carrier has a first surface and a second surface. The first metal layer is disposed on the first surface of the carrier. The circuit layer is disposed on the first metal layer. The dielectric layer covers the circuit layer and defines a plurality of openings to expose portions of the circuit layer and portions of the first metal layer.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: November 19, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Yu-Ying Lee
  • Eye tracking apparatus and method thereof
    Patent number: 10474231
    Abstract: An eye tracking apparatus and an eye tracking method for the eye tracking apparatus are provided. The eye tracking apparatus includes an image capture device and a computing device. The image capture device is adapted to capture at least one face image. The computing device is coupled to the image capture device. The computing device receives the face image to obtain an eye image and identifies at least one iris region of the eye image. The computing device chooses the largest iris region from the iris regions to obtain a fitting pattern of the largest iris region and obtains a gaze point of the eye image based on the fitting pattern.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: November 12, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Hsiao-Wei Liu, Yu-Ying Lan, Hsin-Cheng Lin, Chung-Lun Kuo, Chia-Liang Yeh
  • Tetravalent anti-PSGL-1 antibodies and uses thereof
    Patent number: 10472422
    Abstract: Provided herein are tetravalent antibodies that specifically bind to human PSGL-1. Unlike bivalent antibodies, these tetravalent antibodies contain a dimer of two monomers, with each monomer comprising two light chain variable (VL) domains and two heavy chain variable (VH) domains. This format allows for cross-linker/FcR-expressing cell-independent tetravalent antibodies against PSGL-1 that show enhanced efficacy as compared to bivalent PSGL-1 antibodies. These tetravalent antibodies can be used in a variety of diagnostic and therapeutic methods, including without limitation treating T-cell mediated inflammatory diseases, transplantations, and transfusions.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: November 12, 2019
    Assignees: ABGENOMICS INTERNATIONAL INC., BIOALLIANCE C.V.
    Inventors: Rong-Hwa Lin, Shih-Yao Lin, Yu-Ying Tsai
  • Display device and manufacturing method thereof
    Patent number: 10459566
    Abstract: A touch display panel includes a first patterned metal layer and a second patterned metal layer. The first patterned metal layer includes a first signal line and one or more first segments. The second patterned metal layer is disposed above the first patterned metal layer and includes a second signal line and one or more second segments, wherein the one or more second segments are electrically connected to the one or more first segments such that the one or more first segments and the one or more second segments collectively form at least a part of a touch sensing line.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: October 29, 2019
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Yu-Ying Tang, Chih-Chang Lai
  • Semiconductor device package with a conductive post
    Patent number: 10446411
    Abstract: A semiconductor package includes: (1) a substrate; (2) a first isolation layer disposed on the substrate, the first isolation layer including an opening; (3) a pad disposed on the substrate and exposed from the opening; (4) an interconnection layer disposed on the pad; and (5) a conductive post including a bottom surface, the bottom surface having a first part disposed on the interconnection layer and a plurality of second parts disposed on the first isolation layer.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: October 15, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, Yu-Ying Lee, Yu-Tzu Peng
  • Method for fabricating semiconductor device
    Patent number: 10446667
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; performing a first etching process to form a recess adjacent to the first gate structure; performing an ion implantation process to form an amorphous layer directly under the recess; performing a second etching process to remove the amorphous layer; and forming an epitaxial layer in the recess.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: October 15, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ying Lin, Yi-Liang Ye, Sung-Yuan Tsai, Chun-Wei Yu, Yu-Ren Wang, Zhen Wu, Tai-Yen Lin
  • DYNAMIC MAJOR MODE FOR EFFICIENT MEMORY TRAFFIC CONTROL
    Publication number: 20190303039
    Abstract: An integrated circuit may include a memory controller circuit for communicating with an off-chip memory device. The memory controller is operable in a read-write major mode that is capable of dynamically adapting to any memory traffic pattern, which results in improved memory scheduling efficiency across different user applications. The memory controller may include at least a write command queue, a read command queue, an arbiter, and a command scheduler. The command scheduler may monitor a write command count, a read command count, a write stall count, and a read stall count to determine whether to dynamically adjust a read burst threshold setting and a write burst threshold setting.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Chee Hak Teh, Yu Ying Ong, Kevin Chao Ing Teoh
  • ELECTRODE MATERIAL FOR SECONDARY BATTERY AND SECONDARY BATTERY
    Publication number: 20190305357
    Abstract: An electrode material for a secondary battery and a secondary battery are provided. The electrode material for the secondary battery includes tin-manganese-nickel-oxide. The secondary battery includes a cathode, an anode, an electrolyte, and a package structure, wherein the anode includes the electrode material for the secondary battery.
    Type: Application
    Filed: June 15, 2018
    Publication date: October 3, 2019
    Applicant: National Tsing Hua University
    Inventors: Yu-Ying Chu, Ying-Chan Hung, Han-Yi Chen, Tri-Rung Yew
  • IR Pattern Characteristics For Active Stereo Matching
    Publication number: 20190303704
    Abstract: Various examples with respect to infrared (IR) patter characteristics for stereo matching are described. A control circuit of an apparatus controls an IR projector to project a patterned IR light. In response, the control circuit receives first data of a left image of a scene from a first camera and second data of a right image of the scene from a second camera. The control circuit then performs stereo matching of the left image and the right image to generate a depth map of the scene. The patterned IR light satisfies one or more characteristic requirements.
    Type: Application
    Filed: March 20, 2019
    Publication date: October 3, 2019
    Inventors: Chao-Chung Cheng, Yu-Ying Wang, Chen-Hao Wei, Cheng-Ming Chen, Liang-Chun Lin
  • Method And Apparatus Of Depth Fusion
    Publication number: 20190306489
    Abstract: Various examples with respect to visual depth sensing with accurate and full-range depth fusion and sensing are described. A control circuit of an apparatus receives a plurality of sensor signals that are heterogeneous in type from a plurality of sensors. The control circuit generates first depth-related information of a scene and second depth-related information of the scene based on the plurality of sensor signals. The control circuit then fuses the first depth-related information and the second depth-related information to generate a fused depth map of the scene.
    Type: Application
    Filed: March 20, 2019
    Publication date: October 3, 2019
    Inventors: Chao-Chung Cheng, Chen-Hao Wei, Cheng-Ming Chen, Yu-Ying Wang, Liang-Chun Lin
  • METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
    Publication number: 20190280106
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; performing a first etching process to form a recess adjacent to the first gate structure; performing an ion implantation process to form an amorphous layer directly under the recess; performing a second etching process to remove the amorphous layer; and forming an epitaxial layer in the recess.
    Type: Application
    Filed: May 7, 2019
    Publication date: September 12, 2019
    Inventors: Yu-Ying Lin, Yi-Liang Ye, Sung-Yuan Tsai, Chun-Wei Yu, Yu-Ren Wang, Zhen Wu, Tai-Yen Lin
  • Polysilicon design for replacement gate technology
    Patent number: 10403736
    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: September 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay Chuang, Kong-Beng Thei, Sheng-Chen Chung, Chiung-Han Yeh, Lee-Wee Teo, Yu-Ying Hsu, Bao-Ru Young
  • METHODS FOR MITIGATING TRANSISTOR AGING TO IMPROVE TIMING MARGINS FOR MEMORY INTERFACE SIGNALS
    Publication number: 20190267062
    Abstract: An integrated circuit is operable to communicate with an external component. The integrated circuit may include driver circuits for outputting clock signals and associated control signals to the external component in accordance with a predetermined interface protocol. The clock signals may toggle more frequently than the associated control signals. To help mitigate potential transistor aging effects that could negatively impact timing margins for the control signals, the control signals may be periodically toggled even during idle periods as allowed by the predetermined interface protocol to help improve timing margins.
    Type: Application
    Filed: May 13, 2019
    Publication date: August 29, 2019
    Applicant: Intel Corporation
    Inventors: Tat Hin Tan, Chee Hak Teh, Tick Sern Loh, Wilfred Wee Kee King, Yu Ying Ong
  • Driver for network timing system
    Patent number: 10394734
    Abstract: Devices and methods of providing drivers for software and hardware systems to avoid additional polling or interrupt mechanisms are provided. An electronic device includes a processor supporting a device driver to perform a data packet receiving operation or data packet transmission operation. The device driver causes the processor to receive one or more data packets to a port of the processor according to a time-synchronization protocol. The device driver polls the DMA feature for a completion status of the storing. The device driver causes the processor to determine a timestamp of the one or more data packets and to complete the data packet receiving operation without the device driver causing the processor to perform a polling operation or an interrupt operation to retrieve the timestamp of the one or more data packets.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 27, 2019
    Assignee: Altera Corporation
    Inventors: Sita Rama Chandrasekhar Mallela, Yu Ying Choo
  • Epitaxial process applying light illumination
    Patent number: 10381228
    Abstract: An epitaxial process applying light illumination includes the following steps. A substrate is provided. A dry etching process and a wet etching process are performed to form a recess in the substrate, wherein an infrared light illuminates while the wet etching process is performed. An epitaxial structure is formed in the recess.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: August 13, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ying Lin, Ted Ming-Lang Guo, Chin-Cheng Chien, Chih-Chien Liu, Hsin-Kuo Hsu, Chin-Fu Lin, Chun-Yuan Wu
  • Semiconductor device and manufacturing method thereof
    Patent number: 10366991
    Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, a cladding layer, and a gate structure. The semiconductor substrate includes fin shaped structures. The isolation structure is disposed between the fin shaped structures. Each of the fin shaped structures includes a first portion disposed above a top surface of the isolation structure and a second portion disposed on the first portion. A width of the second portion is smaller than a width of the first portion. The cladding layer is disposed on the first portion and the second portion of each of the fin shaped structures. The cladding layer includes a curved surface. The gate structure is disposed straddling the fin shaped structures.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: July 30, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsu Ting, Yu-Ying Lin, Yen-Hsing Chen, Chun-Jen Chen, Chun-Wei Yu, Keng-Jen Lin, Yu-Ren Wang
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190221562
    Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, a cladding layer, and a gate structure. The semiconductor substrate includes fin shaped structures. The isolation structure is disposed between the fin shaped structures. Each of the fin shaped structures includes a first portion disposed above a top surface of the isolation structure and a second portion disposed on the first portion. A width of the second portion is smaller than a width of the first portion. The cladding layer is disposed on the first portion and the second portion of each of the fin shaped structures. The cladding layer includes a curved surface. The gate structure is disposed straddling the fin shaped structures.
    Type: Application
    Filed: January 25, 2018
    Publication date: July 18, 2019
    Inventors: Hsu Ting, Yu-Ying Lin, Yen-Hsing Chen, Chun-Jen Chen, Chun-Wei Yu, Keng-Jen Lin, Yu-Ren Wang