Patents by Inventor Yu-Yuan Chen

Yu-Yuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12079341
    Abstract: In one embodiment, an apparatus comprises a processor to: receive a request to configure a secure execution environment for a first workload; configure a first set of secure execution enclaves for execution of the first workload, wherein the first set of secure execution enclaves is configured on a first set of processing resources, wherein the first set of processing resources comprises one or more central processing units and one or more accelerators; configure a first set of secure datapaths for communication among the first set of secure execution enclaves during execution of the first workload, wherein the first set of secure datapaths is configured over a first set of interconnect resources; configure the secure execution environment for the first workload, wherein the secure execution environment comprises the first set of secure execution enclaves and the first set of secure datapaths.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: September 3, 2024
    Assignee: Intel Corporation
    Inventors: Kapil Sood, Ioannis T. Schoinas, Yu-Yuan Chen, Raghunandan Makaram, David J. Harriman, Baiju Patel, Ronald Perez, Matthew E. Hoekstra, Reshma Lal
  • Publication number: 20240146501
    Abstract: A method of monitoring a clock signal of a server is provided. The server includes a phase-locked loop (PLL), a baseboard management controller (BMC), and a light emitting unit. The method includes steps of: A) the server executing a time synchronization service to obtain a synchronization mode that the PLL is operating in, where the synchronization mode is one of a free-run mode, a locked mode, and a holdover mode; B) the server updating the synchronization mode to the BMC when executing the time synchronization service; and C) the BMC storing the synchronization mode and controlling the light emitting unit to display in one of a plurality of displaying manners that corresponds to the synchronization mode.
    Type: Application
    Filed: July 10, 2023
    Publication date: May 2, 2024
    Inventors: Yu-Yuan Chen, Po-Wei Chang, Chi-Hua Li
  • Patent number: 11907389
    Abstract: First data is stored. A request for the first data is received from a communication device over a link established with a communication device. An access control engine comprising circuitry is to control access to the first data to the communication device based on an authentication state of the communication device and a protection state of the link.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: February 20, 2024
    Assignee: Intel Corporation
    Inventors: David J. Harriman, Ioannis T. Schoinas, Kapil Sood, Raghunandan Makaram, Yu-Yuan Chen
  • Publication number: 20240045968
    Abstract: In one embodiment, an apparatus comprises a processor to: receive a request to configure a secure execution environment for a first workload; configure a first set of secure execution enclaves for execution of the first workload, wherein the first set of secure execution enclaves is configured on a first set of processing resources, wherein the first set of processing resources comprises one or more central processing units and one or more accelerators; configure a first set of secure datapaths for communication among the first set of secure execution enclaves during execution of the first workload, wherein the first set of secure datapaths is configured over a first set of interconnect resources; configure the secure execution environment for the first workload, wherein the secure execution environment comprises the first set of secure execution enclaves and the first set of secure datapaths.
    Type: Application
    Filed: October 23, 2023
    Publication date: February 8, 2024
    Applicant: Intel Corporation
    Inventors: Kapil Sood, Ioannis T. Schoinas, Yu-Yuan Chen, Raghunandan Makaram, David J. Harriman, Baiju Patel, Ronald Perez, Matthew E. Hoekstra, Reshma Lal
  • Patent number: 11677730
    Abstract: A device includes a microcontroller, memory including secure memory to store a private key, a set of registers, and an authentication engine. The set of registers includes a write mailbox register and a read mailbox register, and message data is to be written to the write mailbox register by a host system. The message data includes at least a portion of a challenge request, and the challenge request includes a challenge by the host system to authenticity of the device. The authentication engine generates a response to the challenge, where the response includes data to identify attributes of the device and a signature generated using the private key. The authentication engine causes at least a portion of the response to be written to the read mailbox register to be read by the host system.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 13, 2023
    Assignee: Intel Corporation
    Inventors: Yu-Yuan Chen, Wojciech S. Powiertowski, Srikanth Varadarajan, David J. Harriman
  • Patent number: 11658947
    Abstract: A protected link between a first computing device and a second computing device is set up, wherein communication over the protected link is to comply with a communication protocol that allows packets to be reordered during transit. A plurality of packets are generated according to a packet format that ensures the plurality of packets will not be reordered during transmission over the protected link, the plurality of packets comprising a first packet and a second packet. Data of the plurality of packets are encrypted for transmission over the protected link, wherein data of the first packet is encrypted based on the cryptographic key and a first value of a counter and data of the second packet is encrypted based on the cryptographic key and a second value of the counter.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: May 23, 2023
    Assignee: Intel Corporation
    Inventors: David J. Harriman, Raghunandan Makaram, Ioannis T. Schoinas, Kapil Sood, Yu-Yuan Chen, Vedvyas Shanbhogue, Siddhartha Chhabra, Reshma Lal, Reouven Elbaz
  • Publication number: 20220350912
    Abstract: First data is stored. A request for the first data is received from a communication device over a link established with a communication device. An access control engine comprising circuitry is to control access to the first data to the communication device based on an authentication state of the communication device and a protection state of the link.
    Type: Application
    Filed: May 16, 2022
    Publication date: November 3, 2022
    Applicant: Intel Corporation
    Inventors: David J. Harriman, Ioannis T. Schoinas, Kapil Sood, Raghunandan Makaram, Yu-Yuan Chen
  • Patent number: 11361093
    Abstract: First data is stored. A request for the first data is received from a communication device over a link established with a communication device. An access control engine comprising circuitry is to control access to the first data to the communication device based on an authentication state of the communication device and a protection state of the link.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: June 14, 2022
    Assignee: Intel Corporation
    Inventors: David J. Harriman, Ioannis T. Schoinas, Kapil Sood, Raghunandan Makaram, Yu-Yuan Chen
  • Publication number: 20220019667
    Abstract: In one embodiment, an apparatus comprises a processor to: receive a request to configure a secure execution environment for a first workload; configure a first set of secure execution enclaves for execution of the first workload, wherein the first set of secure execution enclaves is configured on a first set of processing resources, wherein the first set of processing resources comprises one or more central processing units and one or more accelerators; configure a first set of secure datapaths for communication among the first set of secure execution enclaves during execution of the first workload, wherein the first set of secure datapaths is configured over a first set of interconnect resources; configure the secure execution environment for the first workload, wherein the secure execution environment comprises the first set of secure execution enclaves and the first set of secure datapaths.
    Type: Application
    Filed: June 22, 2021
    Publication date: January 20, 2022
    Applicant: Intel Corporation
    Inventors: Kapil Sood, Ioannis T. Schoinas, Yu-Yuan Chen, Raghunandan Makaram, David J. Harriman, Baiju Patel, Ronald Perez, Matthew E. Hoekstra, Reshma Lal
  • Publication number: 20210344653
    Abstract: A protected link between a first computing device and a second computing device is set up, wherein communication over the protected link is to comply with a communication protocol that allows packets to be reordered during transit. A plurality of packets are generated according to a packet format that ensures the plurality of packets will not be reordered during transmission over the protected link, the plurality of packets comprising a first packet and a second packet. Data of the plurality of packets are encrypted for transmission over the protected link, wherein data of the first packet is encrypted based on the cryptographic key and a first value of a counter and data of the second packet is encrypted based on the cryptographic key and a second value of the counter.
    Type: Application
    Filed: July 7, 2021
    Publication date: November 4, 2021
    Applicant: Intel Corporation
    Inventors: David J. Harriman, Raghunandan Makaram, Ioannis T. Schoinas, Kapil Sood, Yu-Yuan Chen, Vedvyas Shanbhogue, Siddhartha Chhabra, Reshma Lal, Reouven Elbaz
  • Patent number: 11070527
    Abstract: A protected link between a first computing device and a second computing device is set up, wherein communication over the protected link is to comply with a communication protocol that allows packets to be reordered during transit. A plurality of packets are generated according to a packet format that ensures the plurality of packets will not be reordered during transmission over the protected link, the plurality of packets comprising a first packet and a second packet. Data of the plurality of packets are encrypted for transmission over the protected link, wherein data of the first packet is encrypted based on the cryptographic key and a first value of a counter and data of the second packet is encrypted based on the cryptographic key and a second value of the counter.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: July 20, 2021
    Assignee: Intel Corporation
    Inventors: David J. Harriman, Raghunandan Makaram, Ioannis T. Schoinas, Kapil Sood, Yu-Yuan Chen, Vedvyas Shanbhogue, Siddhartha Chhabra, Reshma Lal, Reouven Elbaz
  • Patent number: 11048800
    Abstract: In one embodiment, an apparatus comprises a processor to: receive a request to configure a secure execution environment for a first workload; configure a first set of secure execution enclaves for execution of the first workload, wherein the first set of secure execution enclaves is configured on a first set of processing resources, wherein the first set of processing resources comprises one or more central processing units and one or more accelerators; configure a first set of secure datapaths for communication among the first set of secure execution enclaves during execution of the first workload, wherein the first set of secure datapaths is configured over a first set of interconnect resources; configure the secure execution environment for the first workload, wherein the secure execution environment comprises the first set of secure execution enclaves and the first set of secure datapaths.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: June 29, 2021
    Assignee: Intel Corporation
    Inventors: Kapil Sood, Ioannis T. Schoinas, Yu-Yuan Chen, Raghunandan Makaram, David J. Harriman, Baiju Patel, Ronald Perez, Matthew E. Hoekstra, Reshma Lal
  • Patent number: 10838758
    Abstract: Disclosed is a system comprising a physical memory, a processor and a software component. The software component includes a policy/domain handler for receiving data and a policy associated with the data; a hypervisor; and a file management module. The file management module receives a request from a third-party application to interact with a data file containing the data; sends an authorization and tag request to the policy/domain handler to check if the user and application are permitted to access the data, and if permitted, to generate hardware tags for the data file; and sends a secure data request to the hypervisor to create a secure data compartment for the data file and the hardware tags. Based on the authorization and tag request, and the security policy associated with the data, the policy/domain handler generates the hardware tags for the data file.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: November 17, 2020
    Assignee: Teleputers, LLC
    Inventors: Ruby B. Lee, Pramod A. Jamkhedkar, Yu-Yuan Chen
  • Patent number: 10804761
    Abstract: The present disclosure provides a rotor mechanism includes a rotor core and a plurality of rotor bars. The rotor core has a plurality of insertion slots arranged along an edge of the rotor core. Each of the plurality of rotor bars has an insertion portion and two protruding portions. The insertion portions are respectively located in the plurality of insertion slots, wherein in each of the plurality of rotor bars, the two protruding portions are respectively connected to two opposite ends of the insertion portion and respectively protrude from two opposite sides of the rotor core, and the two protruding portions each has an extension direction, that has an angle with respect to an extension direction of the insertion portion, in order to clamp and fix the rotor core therebetween. In addition, the present disclosure also provides a method for manufacturing the rotor mechanism.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: October 13, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Hsun Wu, Ming-Mao Hsu, Yu-Yuan Chen
  • Publication number: 20190281025
    Abstract: A protected link between a first computing device and a second computing device is set up, wherein communication over the protected link is to comply with a communication protocol that allows packets to be reordered during transit. A plurality of packets are generated according to a packet format that ensures the plurality of packets will not be reordered during transmission over the protected link, the plurality of packets comprising a first packet and a second packet. Data of the plurality of packets are encrypted for transmission over the protected link, wherein data of the first packet is encrypted based on the cryptographic key and a first value of a counter and data of the second packet is encrypted based on the cryptographic key and a second value of the counter.
    Type: Application
    Filed: April 1, 2019
    Publication date: September 12, 2019
    Applicant: Intel Corporation
    Inventors: David J. Harriman, Raghunandan Makaram, Ioannis T. Schoinas, Kapil Sood, Yu-Yuan Chen, Vedvyas Shanbhogue, Siddhartha Chhabra, Reshma Lal, Reouven Elbaz
  • Patent number: 10381888
    Abstract: A motor driving method is applied to a motor with a rotor comprising a magnetic reluctance structure. The motor driving method comprises enabling the motor by an asynchronous driving method, controlling the motor by the asynchronous driving method according to a speed regulation command, detecting a rotor speed of the motor and determining whether the rotor speed is larger than a speed threshold, and when the rotor speed is larger than the speed threshold, controlling the motor by a synchronous driving method.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: August 13, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ming-Mao Hsu, Yu-Yuan Chen, Tsu-Min Liu
  • Publication number: 20190220601
    Abstract: In one embodiment, an apparatus comprises a processor to: receive a request to configure a secure execution environment for a first workload; configure a first set of secure execution enclaves for execution of the first workload, wherein the first set of secure execution enclaves is configured on a first set of processing resources, wherein the first set of processing resources comprises one or more central processing units and one or more accelerators; configure a first set of secure datapaths for communication among the first set of secure execution enclaves during execution of the first workload, wherein the first set of secure datapaths is configured over a first set of interconnect resources; configure the secure execution environment for the first workload, wherein the secure execution environment comprises the first set of secure execution enclaves and the first set of secure datapaths.
    Type: Application
    Filed: March 22, 2019
    Publication date: July 18, 2019
    Applicant: Intel Corporation
    Inventors: Kapil Sood, Ioannis T. Schoinas, Yu-Yuan Chen, Raghunandan Makaram, David J. Harriman, Baiju Patel, Ronald Perez, Matthew E. Hoekstra, Reshma Lal
  • Publication number: 20190220617
    Abstract: First data is stored. A request for the first data is received from a communication device over a link established with a communication device. An access control engine comprising circuitry is to control access to the first data to the communication device based on an authentication state of the communication device and a protection state of the link.
    Type: Application
    Filed: March 27, 2019
    Publication date: July 18, 2019
    Applicant: Intel Corporation
    Inventors: David J. Harriman, Ioannis T. Schoinas, Kapil Sood, Raghunandan Makaram, Yu-Yuan Chen
  • Publication number: 20190190327
    Abstract: A motor driving method is applied to a motor with a rotor comprising a magnetic reluctance structure. The motor driving method comprises enabling the motor by an asynchronous driving method, controlling the motor by the asynchronous driving method according to a speed regulation command, detecting a rotor speed of the motor and determining whether the rotor speed is larger than a speed threshold, and when the rotor speed is larger than the speed threshold, controlling the motor by a synchronous driving method.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 20, 2019
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ming-Mao HSU, Yu-Yuan CHEN, Tsu-Min LIU
  • Publication number: 20190171476
    Abstract: Disclosed is a system comprising a physical memory, a processor and a software component. The software component includes a policy/domain handler for receiving data and a policy associated with the data; a hypervisor; and a file management module. The file management module receives a request from a third-party application to interact with a data file containing the data; sends an authorization and tag request to the policy/domain handler to check if the user and application are permitted to access the data, and if permitted, to generate hardware tags for the data file; and sends a secure data request to the hypervisor to create a secure data compartment for the data file and the hardware tags. Based on the authorization and tag request, and the security policy associated with the data, the policy/domain handler generates the hardware tags for the data file.
    Type: Application
    Filed: January 22, 2019
    Publication date: June 6, 2019
    Applicant: Teleputers, LLC
    Inventors: Ruby B. Lee, Pramod A. Jamkhedkar, Yu-Yuan Chen