Patents by Inventor Yu-Yuan Shen
Yu-Yuan Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7834357Abstract: A structure of a thin film transistor (TFT) is provided. A substrate has a first surface and a second surface opposite to each other, in which the first surface has a patterned mask layer. A patterned first electrode layer is disposed on the second surface of the substrate and has a gate portion and a capacitor electrode portion. A patterned second electrode layer is disposed on the second surface of the substrate and has a source and a drain, in which the patterned second electrode layer is self-aligned with the patterned first electrode layer by exposing the first surface of the substrate with the patterned mask layer as a mask. An insulating layer is disposed between the patterned first electrode layer and the patterned second electrode layer.Type: GrantFiled: October 11, 2007Date of Patent: November 16, 2010Assignee: Industrial Technology Research InstituteInventors: Yi-Kai Wang, Liang-Ying Huang, Tarng-Shiang Hu, Yu-Yuan Shen
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Patent number: 7829398Abstract: A method for making a thin film transistor (TFT) is provided. A mask is first formed on the backside of a substrate, and is used to fabricate a gate, source, and drain of the transistor by backside exposure, such that the source and drain can be self-aligned with the gate pattern. In this way, an alignment shift due to expansion or contraction after performing a high temperature process on an insulating layer can be avoided. Further, since the backside mask previously formed on the substrate can be shifted with the expansion or contraction of the substrate, the process is simplified. Moreover, the source/drain can be accurately aligned with the gate, so that parasitic capacitance can be reduced and flickering of the panel can be avoided.Type: GrantFiled: October 11, 2007Date of Patent: November 9, 2010Assignee: Industrial Technology Research InstituteInventors: Yi-Kai Wang, Liang-Ying Huang, Tarng-Shiang Hu, Yu-Yuan Shen
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Patent number: 7638374Abstract: A method of fabricating a vertical thin film transistor (vertical TFT) is disclosed, wherein a shadow mask is used to fabricate the TFT device in vertical structure. First, a metal layer is formed, which serves as ribs and a gate layer. Next, a shadow mask is disposed on the gate layer. Afterwards, the shadow mask is used as a mask to form a source layer, an organic semiconductor layer and a drain layer. Thus, the process is simplified. Since no photolithography process is required, and therefore damage of the organic semiconductor layer is avoided and a vertical TFT with desired electrical characteristics may be obtained.Type: GrantFiled: August 6, 2009Date of Patent: December 29, 2009Assignee: Industrial Technology Research InstituteInventors: Yi-Kai Wang, Tsung-Hsien Lin, Tarng-Shiang Hu, Yu-Yuan Shen
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Publication number: 20090298241Abstract: A method of fabricating a vertical thin film transistor (vertical TFT) is disclosed, wherein a shadow mask is used to fabricate the TFT device in vertical structure. First, a metal layer is formed, which serves as ribs and a gate layer. Next, a shadow mask is disposed on the gate layer. Afterwards, the shadow mask is used as a mask to form a source layer, an organic semiconductor layer and a drain layer. Thus, the process is simplified. Since no photolithography process is required, and therefore damage of the organic semiconductor layer is avoided and a vertical TFT with desired electrical characteristics may be obtained.Type: ApplicationFiled: August 6, 2009Publication date: December 3, 2009Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yi-Kai Wang, Tsung-Hsien Lin, Tarng-Shiang Hu, Yu-Yuan Shen
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Patent number: 7588971Abstract: A method of fabricating a vertical thin film transistor (vertical TFT) is disclosed, wherein a shadow mask is used to fabricate the TFT device in vertical structure. First, a metal layer is formed, which serves as ribs and a gate layer. Next, a shadow mask is disposed on the gate layer. Afterwards, the shadow mask is used as a mask to form a source layer, an organic semiconductor layer and a drain layer. Thus, the process is simplified. Since no photolithography process is required, and therefore damage of the organic semiconductor layer is avoided and a vertical TFT with desired electrical characteristics may be obtained.Type: GrantFiled: July 17, 2007Date of Patent: September 15, 2009Assignee: Industrial Technology Research InstituteInventors: Yi-Kai Wang, Tsung-Hsien Lin, Tarng-Shiang Hu, Yu-Yuan Shen
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Publication number: 20080102567Abstract: A method for making a thin film transistor (TFT) is provided. A mask is first formed on the backside of a substrate, and is used to fabricate a gate, source, and drain of the transistor by backside exposure, such that the source and drain can be self-aligned with the gate pattern. In this way, an alignment shift due to expansion or contraction after performing a high temperature process on an insulating layer can be avoided. Further, since the backside mask previously formed on the substrate can be shifted with the expansion or contraction of the substrate, the process is simplified. Moreover, the source/drain can be accurately aligned with the gate, so that parasitic capacitance can be reduced and flickering of the panel can be avoided.Type: ApplicationFiled: October 11, 2007Publication date: May 1, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yi-Kai Wang, Liang-Ying Huang, Tarng-Shiang Hu, Yu-Yuan Shen
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Publication number: 20080099843Abstract: A structure of a thin film transistor (TFT) is provided. A substrate has a first surface and a second surface opposite to each other, in which the first surface has a patterned mask layer. A patterned first electrode layer is disposed on the second surface of the substrate and has a gate portion and a capacitor electrode portion. A patterned second electrode layer is disposed on the second surface of the substrate and has a source and a drain, in which the patterned second electrode layer is self-aligned with the patterned first electrode layer by exposing the first surface of the substrate with the patterned mask layer as a mask. An insulating layer is disposed between the patterned first electrode layer and the patterned second electrode layer.Type: ApplicationFiled: October 11, 2007Publication date: May 1, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yi-Kai Wang, Liang-Ying Huang, Tarng-Shiang Hu, Yu-Yuan Shen
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Publication number: 20080014686Abstract: A method of fabricating a vertical thin film transistor (vertical TFT) is disclosed, wherein a shadow mask is used to fabricate the TFT device in vertical structure. First, a metal layer is formed, which serves as ribs and a gate layer. Next, a shadow mask is disposed on the gate layer. Afterwards, the shadow mask is used as a mask to form a source layer, an organic semiconductor layer and a drain layer. Thus, the process is simplified. Since no photolithography process is required, and therefore damage of the organic semiconductor layer is avoided and a vertical TFT with desired electrical characteristics may be obtained.Type: ApplicationFiled: July 17, 2007Publication date: January 17, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yi-Kai Wang, Tsung-Hsien Lin, Tarng-Shiang Hu, Yu-Yuan Shen