Patents by Inventor Yu-Yun Wang

Yu-Yun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240170323
    Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mrunal Abhijith KHADERBAD, Ko-Feng Chen, Zheng-Yong Liang, Chen-Han Wang, De-Yang Chiou, Yu-Yun Peng, Keng-Chu Lin
  • Patent number: 11972974
    Abstract: An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: April 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li Wang, Shuen-Shin Liang, Yu-Yun Peng, Fang-Wei Lee, Chia-Hung Chu, Mrunal Abhijith Khaderbad, Keng-Chu Lin
  • Publication number: 20240110208
    Abstract: A gene editing system of Candida viswanathii includes a Candida viswanathii, a first gene editing fragment and a second gene editing fragment. The first gene editing fragment successively includes a first homology arm and a screening gene. The second gene editing fragment is connected to a C-terminus of the first gene editing fragment and includes a second homology arm, a Cas9 expression cassette and a sgRNA cassette. The Cas9 expression cassette successively includes a Cas9 promoter, a Cas9 gene and three nuclear localization sequences. The sgRNA cassette successively includes a sgRNA promoter, a first ribozyme, a targeting sequence, a scaffold and a second ribozyme. The first gene editing fragment and the second gene editing fragment are constructed as a linear fragment for gene editing of a chromosome of the Candida viswanathii.
    Type: Application
    Filed: March 24, 2023
    Publication date: April 4, 2024
    Inventors: Yu-Chen HU, Nam Ngoc PHAM, June-Yen CHOU, Hsing-Yun WANG, Vincent Jianan LIU
  • Patent number: 11945918
    Abstract: This invention relates to the field of contaminated plastic waste decomposition. More specifically, the invention comprises methods and systems to decompose contaminated plastic waste and transform it into value-added products.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: April 2, 2024
    Assignee: Novoloop, Inc.
    Inventors: Jia Yun Yao, Yu Wen Wang, Tapaswy Muppaneni, Ruja Shrestha, Jennifer Le Roy, Garret D. Figuly
  • Patent number: 11942358
    Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices. The method includes forming, on a substrate, first and second fin structures with an opening in between, filling the opening with a flowable isolation material, treating the flowable isolation material with a plasma, and removing a portion of the plasma-treated flowable isolation material between the first and second fin structures.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal Abhijith Khaderbad, Ko-Feng Chen, Zheng-Yong Liang, Chen-Han Wang, De-Yang Chiou, Yu-Yun Peng, Keng-Chu Lin
  • Publication number: 20240098960
    Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 21, 2024
    Inventors: YU-KUAN LIN, CHANG-TA YANG, PING-WEI WANG, KUO-YI CHAO, MEI-YUN WANG
  • Publication number: 20180190845
    Abstract: A compound-based solar cell including a first electrode, a second electrode, a first type doped semiconductor layer and a second type doped semiconductor layer is provided. The first type doped semiconductor layer is disposed between the first electrode and the second electrode, and the second type doped semiconductor layer is disposed between the first type doped semiconductor layer and the second electrode. The first type doped semiconductor layer has a first side adjacent to the first electrode and a second side adjacent to the second type doped semiconductor layer. The first type doped semiconductor layer includes at least one of a plurality of elements, and the elements include potassium, rubidium and cesium. The concentration of at least one of the elements on the first side is higher than the concentration on the second side. Besides, a manufacturing method of a light absorption layer is also provided.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Applicant: Industrial Technology Research Institute
    Inventors: Lung-Teng Cheng, Yu-Yun Wang, Tung-Po Hsieh
  • Patent number: 8828767
    Abstract: The disclosure discloses a fabrication method for a light absorption layer of a solar cell, including: forming a precursor film on a substrate, wherein the precursor film includes the Group IB-IIB-IVA-VIA amorphous nanoparticles; and conducting a thermal process to the precursor film to form the light absorption layer on the substrate.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: September 9, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Tsung-Shin Wu, Shih-Hsiung Wu, Hung-Chun Pan, Lung-Teng Cheng, Yu-Yun Wang
  • Publication number: 20140179048
    Abstract: A method for preparing an absorbing layer of a solar cell includes the following steps. An absorbing layer precursor containing at least one group XIV element is loaded on a substrate. A solid vapor source containing a group XIV element, the same as the group XIV element in the absorbing layer precursor is provided. The solid vapor source corresponds to the absorbing layer precursor. The solid vapor source and the absorbing layer precursor are kept apart by a distance. A heating process is performed so that the absorbing layer precursor forms an absorbing layer, the solid vapor source is vaporized and generates a gas containing the group XIV element, and the gas containing the group XIV element inhibits the effusion of the group XIV element of the absorbing layer precursor so that the proportion of the group XIV element in the formed absorbing layer is consistent.
    Type: Application
    Filed: June 3, 2013
    Publication date: June 26, 2014
    Inventors: Tzung-Shin Wu, Shih-Hsiung Wu, Yu-Yun Wang, Hung-Ru Hsu, Ho-Min Chen
  • Publication number: 20130171768
    Abstract: The disclosure discloses a fabrication method for a light absorption layer of a solar cell, including: forming a precursor film on a substrate, wherein the precursor film includes the Group IB-IIB-IVA-VIA amorphous nanoparticles; and conducting a thermal process to the precursor film to form the light absorption layer on the substrate.
    Type: Application
    Filed: August 31, 2012
    Publication date: July 4, 2013
    Inventors: Tsung-Shin Wu, Shih-Hsiung Wu, Hung-Chun Pan, Lung-Teng Cheng, Yu-Yun Wang
  • Publication number: 20130017322
    Abstract: An embodiment of the invention provides a method for forming an indium (III) sulfide film, including providing a mixed solution containing a complexing agent, indium ions, and hydrogen sulfide ions; and contacting the mixed solution with a substrate to form an indium (III) sulfide film thereon, wherein the complexing agent has the following formula: wherein each of R1 and R2 respectively is hydrogen or hydroxyl.
    Type: Application
    Filed: November 25, 2011
    Publication date: January 17, 2013
    Inventors: Chung-Shin WU, Yu-Yun Wang, Pei-Sun Sheng