Patents by Inventor Yu Ze Lin

Yu Ze Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250103786
    Abstract: An integrated circuit design implementation system includes a die-to-die (D2D) complier configured to receive a configuration of a semiconductor package. The semiconductor package includes a first semiconductor die and a second semiconductor die bonded to each other. The D2D compiler is configured to generate, based on the configuration of the semiconductor package, a first bump map and a second bump map for the first semiconductor die and the second semiconductor die, respectively. The first bump map indicates respective locations of a plurality of first bump structures of the first semiconductor die, and the second bump map indicates respective locations of a plurality of second bump structures of the second semiconductor die.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Chia Chen, Yu-Ze Lin, Huang-Yu Chen, King-Ho Tam, Chen-Jih Lui, Tze-Chiang Huang, Sandeep Kumar Goel
  • Publication number: 20240303409
    Abstract: A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device, subject to a limiting condition, such as one determined using a cost function. A computer system including one or more EDAs configured to perform the method is also disclosed.
    Type: Application
    Filed: May 21, 2024
    Publication date: September 12, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Chi Chen, King-Ho Tam, Yu-Ze Lin, Huang-Yu Chen
  • Patent number: 12001773
    Abstract: A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device, subject to a limiting condition, such as one determined using a cost function. A computer system including one or more EDAs configured to perform the method is also disclosed.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shin-Chi Chen, King-Ho Tam, Yu-Ze Lin, Huang-Yu Chen
  • Publication number: 20230237238
    Abstract: A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device, subject to a limiting condition, such as one determined using a cost function. A computer system including one or more EDAs configured to perform the method is also disclosed.
    Type: Application
    Filed: April 3, 2023
    Publication date: July 27, 2023
    Inventors: Shin-Chi Chen, King-Ho Tam, Yu-Ze Lin, Huang-Yu Chen
  • Patent number: 11620426
    Abstract: A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device. A computer system including one or more EDAs configured to perform the method is also disclosed.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: April 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shin-Chi Chen, King-Ho Tam, Yu-Ze Lin, Huang-Yu Chen
  • Publication number: 20220382946
    Abstract: A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device. A computer system including one or more EDAs configured to perform the method is also disclosed.
    Type: Application
    Filed: May 27, 2021
    Publication date: December 1, 2022
    Inventors: Shin-Chi Chen, King-Ho Tam, Yu-Ze Lin, Huang-Yu Chen
  • Patent number: 9334560
    Abstract: A cutting tool having a metallic glass thin film (MGTF) coated thereon, a metallic glass cutting tool, and methods of fabricating the same are disclosed. The cutting tool having metallic glass thin film coated thereon comprises: a cutting element having a sharpened portion, and the cutting element is made of metal; and a metallic glass thin film coated on the cutting element, and the metallic glass is represented by the following formula 1 or formula 2, (ZraCubNicAld)100-xSix,??[formula 1] wherein 45=<a=<75, 25=<b=<35, 5=<c=<15, 5=<d=<15, 0.1=<x=<10, (ZreCufAggAlh)100-ySiy,??[formula 2] 35=<e=<55, 35=<f=<55, 5=<g=<15, 5=<h=<15, 0.1=<y=<10. The metallic glass cutting tool of the present invention comprises: a cutting element having a sharpened portion, and the cutting element is made of a metallic glass represented by the above formula 1 or formula 2.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: May 10, 2016
    Assignee: National Central University
    Inventors: Jason Shiang Ching Jang, Pei Hua Tsai, Jia Bin Li, Yu Ze Lin, Chih Chiang Fu, Jinn P. Chu
  • Publication number: 20140353139
    Abstract: A cutting tool having a metallic glass thin film (MGTF) coated thereon, a metallic glass cutting tool, and methods of fabricating the same are disclosed. The cutting tool having metallic glass thin film coated thereon comprises: a cutting element having a sharpened portion, and the cutting element is made of metal; and a metallic glass thin film coated on the cutting element, and the metallic glass is represented by the following formula 1 or formula 2, (ZraCubNicAld)100-xSix,??[formula 1] wherein 45=<a=<75, 25=<b=<35, 5=<c=<15, 5=<d=<15, 0.1=<x=<10, (ZreCufAggAlh)100-ySiy,??[formula 2] 35=<e=<55, 35=<f=<55, 5=<g=<15, 5=<h=<15, 0.1=<y=<10. The metallic glass cutting tool of the present invention comprises: a cutting element having a sharpened portion, and the cutting element is made of a metallic glass represented by the above formula 1 or formula 2.
    Type: Application
    Filed: August 19, 2014
    Publication date: December 4, 2014
    Inventors: Jason Shiang Ching JANG, Pei Hua TSAI, Jia Bin LI, Yu Ze LIN, Chih Chiang FU, Jinn P. CHU
  • Publication number: 20130108888
    Abstract: A cutting tool having a metallic glass thin film (MGTF) coated thereon, a metallic glass cutting tool, and methods of fabricating the same are disclosed. The cutting tool having metallic glass thin film coated thereon comprises: a cutting element having a sharpened portion, and the cutting element is made of metal; and a metallic glass thin film coated on the cutting element, and the metallic glass is represented by the following formula 1 or formula 2, (ZraCubNicAld)100-xSix,??[formula 1] wherein 45=<a=<75, 25=<b=<35, 5=<c=<15, 5=<d=<15, 0.1=<x=<10, (ZreCufAggAlh)100-ySiy,??[formula 2] 35=<e=<55, 35=<f=<55, 5=<g=<15, 5=<h=<15, 0.1=<y=<10. The metallic glass cutting tool of the present invention comprises: a cutting element having a sharpened portion, and the cutting element is made of a metallic glass represented by the above formula 1 or formula 2.
    Type: Application
    Filed: September 6, 2012
    Publication date: May 2, 2013
    Inventors: Jason Shiang Ching JANG, Pei Hua TSAI, Jia Bin LI, Yu Ze Lin, Chih Chiang FU, Jinn P. CHU