Abstract: A gel composition, in particular a gelled electrolyte, comprising: i) fumed alumina particles, wherein the mean primary particle size of the particle is from 5 to 50 nm and the BET specific surface area is from 40 to 400 m2/g; ii) at least two organic solvents; and iii) a lithium salt; wherein the amount of the alumina particles is 0.2-10% by weight based on the total weight of the gel composition. A method to prepare a gelled electrolyte, a Li-ion battery, a Li-ion battery and a device are also provided.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.

Abstract: A radar system transmits pulses towards a target and receives pulses reflected back therefrom. Based on samples (of the received pulses) corresponding to a CPI, a first 2D matrix having a slow-time index and a fast-time index is generated. A slow-time FFT is performed to convert the slow-time index to a Doppler bin index to produce a second 2D matrix having the Doppler bin index and the fast-time index. Thereafter, a 1D interpolation is performed along the Doppler bin index to produce a third 2D matrix having a Velocity bin index and the fast-time index. Thereafter, a fast-time FFT is performed to convert the fast-time index to a Range bin index to produce a fourth 2D matrix having the Velocity bin index and a Range bin index. A distance to and a velocity of a target is determined based on the fourth 2D matrix.

Abstract: A finger for a robotic gripper may include a flexible backbone, a plurality of jamming layers, and a membrane bag. The backbone may have a first side, a second side, a third side, and a fourth side. The backbone may include a flexible beam, and a plurality of branches attached to the flexible beam and spaced apart from one another. Each branch may include a first end surface extending along the first side, and a second end surface extending along the second side. The first end surfaces may collectively extend along a majority of the first side, and the second end surfaces may collectively extend along a majority of the second side. The jamming layers may be positioned along the third side or the fourth side. The membrane bag may be positioned over the jamming layers.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a base structure. The semiconductor device structure also includes a first epitaxial structure and a second epitaxial structure sandwiching the channel structures. The semiconductor device structure further includes a gate stack wrapped around each of the channel structures and a backside conductive contact connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. In addition, the semiconductor device structure includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.

Abstract: A user equipment assistance information (UAI) negotiation method, for a user equipment (UE) of mobile communication includes receiving a first OtherConfig element of an RRC reconfiguration message comprising a plurality of configuration parameters with SETUP values from a network terminal; sending a first UAI including a first value of a first configuration parameter of the configuration parameters to the network terminal; and receiving a first RRC reconfiguration message corresponding to the first UAI from the network terminal.

Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a first source/drain region disposed under a well portion, a second source/drain region disposed adjacent the first source/drain region, a dielectric material disposed between the first and second source/drain regions, and a conductive contact having a first portion disposed under the first source/drain region and a second portion disposed adjacent the first source/drain region. The second portion is disposed in the dielectric material. The structure further includes a conductive feature disposed in the dielectric material, and the conductive feature is electrically connected to the conductive contact. The conductive feature has a top surface that is substantially coplanar with a top surface of the well portion.

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Abstract: The present disclosure relates to a semiconductor device having a backside source/drain contact, and method for forming the device. The semiconductor device includes a source/drain feature having a top surface and a bottom surface, a first silicide layer formed in contact with the top surface of the source/drain feature, a first conductive feature formed on the first silicide layer, and a second conductive feature having a body portion and a first sidewall portion extending from the body portion, wherein the body portion is below the bottom surface of the source/drain feature, and the first sidewall portion is in contact with the first conductive feature.

Abstract: The present invention relates to the fields of microorgan-isms, feed, food and ecological restoration, in particular to a strain for degrading deoxynivalenol (DON) and the use thereof. The strain has the deposit number CCTCC No. M 2020565. The strain can grow by means of taking the toxic compound DON as a sole carbon source, and convert the DON into chemical components for itself. The reaction process is irreversible, the reaction conditions are moderate, and secondary pollu-tion cannot be caused. The strain provided in the present invention can be used for preparing a biological detoxification preparation for DON. The strain provided in the present invention can be used for degrading DON in feed and food raw materials, primary processing products, deep processing products and related processing byproducts. The strain provided in the present invention can be applied to various ecosystems such as soil or bodies of water polluted by DON to achieve the purposes of DON degradation and ecological restoration.

Abstract: A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.

Abstract: A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.

Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.

Abstract: Embodiments of this application provide a composite structure including a substrate layer and a functional layer disposed on a surface of at least one side of the substrate layer. The substrate layer includes a first support member and a second support member that are disposed side by side and a bendable connecting member connected to and disposed between the first support member and the second support member. A material of the first support member and the second support member includes a hard rubber fiber composite material, and the functional layer includes one or more of an electrically conductive layer, a thermally conductive layer, or an impact-resistant layer.

Abstract: Various embodiments include methods and systems having detection apparatus operable to cancel or reduce leakage signal originating from a source signal being generated and transmitted from a transmitter. A leakage cancellation signal can be generated digitally, converted to an analog signal, and then subtracted in the analog domain from a received signal to provide a leakage-reduced signal for use in detection and analysis of objects. A digital cancellation signal may be generated by generating a cancellation signal in the frequency domain and converting it to the time domain. Optionally, an estimate of a residual leakage signal can be generated and applied to reduce residual leakage remaining in the leakage-reduced signal. Additional apparatus, systems, and methods can be implemented in a variety of applications.

Abstract: This present disclosure provides a core-shell quantum dot, a preparation method thereof, and a light-emitting device containing the same. The core of the core-shell quantum dot is CdSeXS(1-X), and the quantum dot shells include a first shell and a second shell, the first shell being selected from one or more of ZnSe, ZnSeYS(1-Y) and Cd(Z)Zn(1-Z)S, the second shell covering the first shell being one of Cd(Z)Zn(1-Z)S and ZnS, the maximum emission peak of the core-shell quantum dot is less than or equal to 480 nm, 0<X<1, 0<Y<1, 0<Z<1. The CdSeXS(1-X) core has a smaller bandgap and a shallower HOMO energy level, making hole injection easier.

Abstract: A method of patterning a semiconductor layer includes the following steps. The semiconductor layer is formed on a substrate. A photoresist layer is formed on the semiconductor layer. The photoresist layer is patterned to form an opening exposing an exposed region of the semiconductor layer. The exposed region of the semiconductor layer is dissolved with a solution to pattern the semiconductor layer, in which the solution includes a first organic solvent and a second organic solvent. The solubility of the semiconductor layer in the first organic solvent is greater than 1 mg/mL, and the solubility of the semiconductor layer in the second organic solvent is less than or equal to 1 mg/mL.

Abstract: In one aspect, the disclosure relates to cooling films comprising a substrate and one or more cooling materials deposited on the substrate. The disclosed cooling films can be used to prepare the disclosed cooling masterbatch materials. The disclosed cooling masterbatch materials can be used to prepare disclosed cooling yarns. The one or more cooling materials deposited on the substrate of a disclosed cooling film, dispersed in a disclosed cooling masterbatch material, or in disclosed cooling yarn are nano-sized particles. In still further aspects, the present disclosure pertains to a fabric comprising a disclosed cooling yarn. This abstract is intended as a scanning tool for purposes of searching in the particular art and is not intended to be limiting of the present disclosure.