Abstract: To realize a highly reliable IGBT that suppresses the bipolar degradation by preventing the occurrence of a defect on a boundary between a contact region and a silicide layer. As a means to realize the above, a semiconductor device includes: a collector region that is formed on a lower surface of a semiconductor substrate and forms an IGBT; and a collector electrode that is formed on a lower surface of the collector region via a silicide layer. The collector region and the silicide layer contains aluminum, first metal being more easily bondable to silicon than aluminum, and second metal being more easily bondable to carbon than aluminum.

Abstract: Dielectric breakdown resistance of a power module including a SiC-IGBT and a SiC diode is improved. The power module includes a SiC-IGBT 110 and a SiC diode 111, and a film thickness of a resin layer 323 covering an upper portion of an electric field relaxation region 320 of the SiC-IGBT 110 is larger than a chip thickness of the SiC-IGBT 110, that is, for example, 200 ?m or more.

Abstract: Dielectric breakdown resistance of a power module including a SiC-IGBT and a SiC diode is improved. The power module includes a SiC-IGBT 110 and a SiC diode 111, and a film thickness of a resin layer 323 covering an upper portion of an electric field relaxation region 320 of the SiC-IGBT 110 is larger than a chip thickness of the SiC-IGBT 110, that is, for example, 200 ?m or more.

Abstract: A silicon carbide semiconductor device includes an n-type silicon carbide semiconductor substrate, a drain electrode electrically connected to a rear face, an n-type semiconductor layer having a second impurity concentration lower than the first impurity concentration, a p-type first semiconductor region, an n-type second semiconductor region, and an n-type third semiconductor region. A trench is formed having a gate electrode therein in which the bottom face of the trench contacts the p-type semiconductor region. A metal layer is electrically connected to the third semiconductor region, and a source electrode electrically connects the second semiconductor region and the metal layer to each other.

Abstract: A silicon carbide semiconductor device includes an n-type silicon carbide semiconductor substrate, a drain electrode electrically connected to a rear face, an n-type semiconductor layer having a second impurity concentration lower than the first impurity concentration, a p-type first semiconductor region, an n-type second semiconductor region, an n-type third semiconductor region, a trench having a first side face and a second side face opposing to each other and a third side face intersecting with the first side face and the second side face, a gate electrode formed in the trench with a gate insulating film interposed therebetween, a metal layer electrically connected to the third semiconductor region, and a source electrode electrically connecting the second semiconductor region and the metal layer to each other.

Abstract: A technology is proposed in which the improvement of the capability of a semiconductor device can be realized by satisfying both reduction of leakage currents and suppression of the degradation of the conductive characteristic of the semiconductor device. An electric field relaxation region ERR is formed in an outer edge region on the outside of a mesa structure MS. In addition, an electric charge implantation region EIR formed on a drift layer EPI, a resistance reduction region RR formed on the electric charge implantation region EIR, and a leakage reduction region LR formed at a sidewall portion of the mesa structure MS are formed in the mesa structure MS. In this case, the impurity concentration of the leakage reduction region LR is set larger than the impurity concentration of the electric field relaxation region ERR, and is set smaller than the impurity concentration of the resistance reduction region RR.

Abstract: A technology is proposed in which the improvement of the capability of a semiconductor device can be realized by satisfying both reduction of leakage currents and suppression of the degradation of the conductive characteristic of the semiconductor device. An electric field relaxation region ERR is formed in an outer edge region on the outside of a mesa structure MS. In addition, an electric charge implantation region EIR formed on a drift layer EPI, a resistance reduction region RR formed on the electric charge implantation region EIR, and a leakage reduction region LR formed at a sidewall portion of the mesa structure MS are formed in the mesa structure MS. In this case, the impurity concentration of the leakage reduction region LR is set larger than the impurity concentration of the electric field relaxation region ERR, and is set smaller than the impurity concentration of the resistance reduction region RR.