Abstract: One embodiment of the present invention provides a system that improves the effectiveness of prefetching during execution of instructions in scout mode. Upon encountering a non-data dependent stall condition, the system performs a checkpoint and commences execution of instructions in scout mode, wherein instructions are speculatively executed to prefetch future memory operations, but wherein results are not committed to the architectural state of a processor. When the system executes a load instruction during scout mode, if the load instruction causes a lower-level cache miss, the system allows the load instruction to access a higher-level cache. Next, the system places the load instruction and subsequent dependent instructions into a deferred queue, and resumes execution of the program in scout mode.

Abstract: A method is disclosed that uses a non-coherent store instruction to reduce inter-thread communication latency between threads sharing a level one write-through cache. When a thread executes the non-coherent store instruction, the level one cache is immediately updated with the data value. The data value is immediately available to another thread sharing the level-one write-through cache. A computer system having reduced inter-thread communication latency is disclosed. The computer system includes a first plurality of processor cores, each processor core including a second plurality of processing engines sharing a level one write-through cache. The level one caches are connected to a level two cache via a crossbar switch. The computer system further implements a non-coherent store instruction that updates a data value in the level one cache prior to updating the corresponding data value in the level two cache.

Abstract: A multi-stride prefetcher includes a recurring prefetch table that in turn includes a stream table and an index table. The stream table includes a valid field and a tag field. The stream table also includes a thread number field to help support multi-threaded processor cores. The tag field stores a tag from an address associated with a cache miss. The index table includes fields for storing information characterizing a state machine. The fields include a learning bit. The multi-stride prefetcher prefetches data into a cache for a plurality of streams of cache misses, each stream having a plurality of strides.

Abstract: One embodiment of the present invention provides a system that performs register file checkpointing to support speculative execution within a processor. During operation, the system commences speculative execution of a program from a point of speculation, at which the outcome of a long latency instruction is speculatively predicted. During this speculative execution, registers are updated by checkpointing an old value of the register, if the register has not already been checkpointed, and then updating the architectural state of the register with the new value. In this way, only registers that are updated during the speculative execution are checkpointed, instead of checkpointing all of the architectural registers prior to commencing speculative execution.

Abstract: A dynamic prediction is made whether a load instruction will miss a cache. Data is prefetched for the load instruction when a cache miss is predicted. Thus, the prefetch is only performed if a trigger event correlated with a cache miss for that load instruction is detected. This selective execution of the prefetches for a particular load instruction improves processor utilization and performance.

Abstract: One embodiment of the present invention provides a system that improves the effectiveness of prefetching during execution of instructions in scout mode. During operation, the system executes program instructions in a normal-execution mode. Upon encountering a condition which causes the processor to enter scout mode, the system performs a checkpoint and commences execution of instructions in scout mode, wherein the instructions are speculatively executed to prefetch future memory operations, but wherein results are not committed to the architectural state of a processor. During execution of a load instruction during scout mode, if the load instruction is a special load instruction and if the load instruction causes a lower-level cache miss, the system waits for data to be returned from a higher-level cache before resuming execution of subsequent instructions in scout mode, instead of disregarding the result of the load instruction and immediately resuming execution in scout mode.

Abstract: Typically, missing read operations instances account for a small fraction of the operations instances of an application, but for nearly all of the performance degradation due to access latency. Hence, a small predictor structure maintains sufficient information for performing value prediction for the small fraction of operations (the missing instances of read operations) that account for nearly all of the access latency performance degradation. With such a small predictor structure, a processor value predicts for selective instances of read operations, those selective instances being read operations that are unavailable in a first memory (e.g., those instances of read operations that miss in L2 cache). Respective actual values for prior missing instances of the read operations are stored and used for value predictions of respective subsequent instances of the read operations.

Abstract: One embodiment of the present invention provides a system that dynamically allocates physical registers in a windowed processor architecture. The system includes a physical register file and a register map that maps architectural registers defined within an executing program to physical registers within the physical register file. The system also includes a window allocation mechanism that allocates a new name space for a register window without allocating physical registers for the register window, thereby allowing the physical registers to be dynamically allocated as needed instead of being allocated at window initialization time.

Abstract: One embodiment of the present invention provides a system that performs register file checkpointing to support speculative execution within a processor. During operation, the system commences speculative execution of a program from a point of speculation, at which the outcome of a long latency instruction is speculatively predicted. During this speculative execution, registers are updated by checkpointing an old value of the register, if the register has not already been checkpointed, and then updating the architectural state of the register with the new value. In this way, only registers that are updated during the speculative execution are checkpointed, instead of checkpointing all of the architectural registers prior to commencing speculative execution.

Abstract: One embodiment of the present invention provides a system that dynamically allocates physical registers in a windowed processor architecture. The system includes a physical register file and a register map that maps architectural registers defined within an executing program to physical registers within the physical register file. The system also includes a window allocation mechanism that allocates a new name space for a register window without allocating physical registers for the register window, thereby allowing the physical registers to be dynamically allocated as needed instead of being allocated at window initialization time.