Abstract: Provided is a light-emitting quantum dot coated with at least one blue-light absorption layer, including an alloy core consisting of Cd, Se, Zn, and S, at least one first shell layer which has a wurtzite structure and is coated on a surface of the alloy core; and a second shell layer consisting of ZnS and, having a zinc blende structure and is coated on a surface of the first shell layer, wherein the element ratio of each of Zn and S accounts for 30 to 50% of the overall core, and the content of Cd and Se gradually decreases outward from the core center. Also provided is a method for preparing the core-shell type light-emitting quantum dot.

Abstract: A front light module provided includes a light-emitting element, a light guide plate, and a film assembly. The light guide plate has a light-incident surface and a light-exiting surface. The light-incident surface is connected to the light-exiting surface and is disposed opposite to the light-emitting element. The light-exiting surface has a plurality of microstructures. The film assembly includes a first light-penetrating adhesive layer, an optical film, and a second light-penetrating adhesive layer. The first light-penetrating adhesive layer is connected to the light-exiting surface. The optical film is disposed between the first light-penetrating adhesive layer and the second light-penetrating adhesive layer, and the first light-penetrating adhesive layer is disposed between the light guide plate and the optical film. A display device having the front light module is also provided. The front light module and the display device can improve the visibility.

Abstract: A manufacturing method of an electronic package includes the following steps. A first interfacial dielectric layer is formed to cover sides of multiple first conductive vias and multiple second conductive vias. Multiple chips are directly bonded to the first and second conductive vias. A base dielectric layer is formed to fill a gap between the adjacent chips. A bridge element is directly bonded to the first conductive vias, such that the bridge element partially overlaps the adjacent chips respectively. A second interfacial dielectric layer and multiple third conductive vias are formed on the first interfacial dielectric layer and the bridge element. A redistribution circuit structure is formed on the second interfacial dielectric layer and the third conductive vias. Multiple conductive bumps are formed on the redistribution circuit structure. An electronic package is also provided.

Abstract: A light-emitting diode chip includes a substrate. The substrate has a side surface configured as a serrated surface, which includes a plurality of laser inscribed features disposed along a thickness direction of the substrate and spaced apart from each other. A method for manufacturing the light-emitting diode chip is also disclosed herein.

Abstract: A level shifter includes a cross-coupled transistor pair, first through third biased transistor pairs and a differential input pair sequentially coupled in series, and further includes a sub level shifter. The first biased transistor pair is controlled by a first reference voltage. The second biased transistor pair is controlled by a pair of differential control voltages. The third biased transistor pair is controlled by a second reference voltage lower than the first reference voltage. The differential input pair is controlled by a pair of differential input voltages. The sub level shifter generates the differential control voltages according to the differential input voltages and the first and second reference voltages. The differential control voltages are switched between the first and second reference voltages. The level shifter outputs a pair of differential output voltages through inverted and non-inverted output terminals coupled with the second biased transistor pair.

Abstract: A method of manufacturing a semiconductor device includes at least the following steps. A protrusion is formed in a substrate by an anisotropic etch process, wherein a sidewall of the protrusion is inclined. A recess is formed on the sidewall of the protrusion by an isotropic etch process, wherein during the isotropic etch process, a by-product covers a first portion of the sidewall of the protrusion while exposing a second portion of the sidewall of the protrusion, so that the recess is formed between the first portion and the second portion of the sidewall.

Abstract: A method includes providing a substrate of a first conductivity type, the substrate including a first circuit region and a second circuit region; forming a first well region of a second conductivity type in the first circuit region of the substrate; forming a first doped region of the second conductivity type in the first well region; forming a diode in the second circuit region of the substrate; forming a first transistor and a second transistor over the substrate in the first circuit region and the second circuit region, respectively; forming a discharge structure over the substrate to electrically couple the first doped region to the diode; and forming a metallization layer over the discharge structure to electrically couple the first transistor to the second transistor subsequent to the forming of the diode, wherein charges accumulated in the first well region are drained to the substrate through the discharge structure.

Abstract: A light-emitting diode and a light-emitting device are provided, relating to the field of semiconductor manufacturing, including a substrate, an epitaxial structure and a Bragg reflective layer. The Bragg reflective layer includes a first film stack and a second film stack alternately and repetitively arranged. The first film stack and the second film stack both include a first material layer with a first refractive index and a second material layer with a second refractive index, the first material layer and the second material layer are alternately stacked repeatedly, and the first refractive index is lower than the second refractive index. In the first film stack, an optical thickness of the first material layer is greater than that of the second material layer. In the second film stack, an optical thickness of the first material layer is less than that of the second material layer.

Abstract: An over-current protection device includes an electrode layer and a heat-sensitive layer. The heat-sensitive layer includes a polymer matrix and a conductive filler. The polymer matrix includes a polyolefin-based polymer and an olefin-acrylate copolymer. The polyolefin-based polymer is represented by a formula (I): ?wherein R1 and R2 are selected from the group consisting of CH3, C2H5, and C3H7. The olefin-acrylate copolymer is represented by a formula (II): ?wherein R is selected from the group consisting of COOCH3, COOC2H5, and COOC4H9.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are disclosed. The semiconductor structure includes a first die including a fuse structure in a topmost layer of the first die, the fuse structure including a pair of conductive segments, wherein one of the pair of conductive segments is electrically connected to a bonding pad of the first die, wherein the bonding pad is electrically connected to ground; and an inductor electrically connected to the one of the pair of conductive segments.

Abstract: A light-emitting diode and a light-emitting device are provided, the light-emitting diode includes a substrate, an epitaxial structure and a Bragg reflector. The Bragg reflector includes first film stacks and second film stacks repeatedly and alternately stacked. The first film stack includes at least one pair layer consisting of a first material layer and a second material layer, an optical thickness of the first material layer is greater than that of the second material layer in each pair layer. The second film stack includes multiple pair layers consisting of a first material layer and a second material layer; and the second film stack is formed by repeatedly and alternately stacking a pair layer with optical thickness of the first material layer greater than that of the second material layer and a pair layer with optical thickness of the first material layer smaller than that of the second material layer.

Abstract: An array of complementary die sets is attached to a carrier substrate. A continuous complementary-level molding compound layer is formed around the array of complementary die sets. An array of primary semiconductor dies is attached to the array of complementary die sets. A continuous primary-level molding compound layer is formed around the array of primary semiconductor dies. The bonded assembly is diced by cutting along directions that are parallel to edges of the primary semiconductor dies. The sidewalls of the complementary dies are azimuthally tilted relative to sidewalls of the primary semiconductor dies, or major crystallographic directions of a single crystalline material in the carrier substrate are azimuthally tilted relative to sidewalls of the primary semiconductor dies.

Abstract: A method for improving transmission power management with compliance to regulations of radiofrequency exposure, which may comprise: at a current time, estimating whether a window average power, which may reflect average power transmitted using a radio technology during a moving time window, will exceed a power limit after the current time; if true, proceeding to at least one of a first handling subroutine and a second handling subroutine to set a power cap, and causing power transmitted to be capped by the power cap after the current time. The first handling subroutine may comprise: scheduling to set the power cap lower at a scheduled time. Estimating whether the window average power will exceed the power limit may involve discarding one of a plurality of power records. The second handling subroutine may comprise: setting the power cap not higher than the discarded one of the plurality of power records.

Abstract: A control circuit is included in a first die of a stacked semiconductor device. The first die further includes a transistor that is electrically connected to the control circuit. The transistor is configured to be controlled by the control circuit to selectively block a die-to-die interconnect. In this way, the die-to-die interconnect may be selectively blocked to isolate the first die and a second die of the stacked semiconductor device for independent testing after bonding. This may increase the effectiveness of a testing to identify and isolate defects in the first die or the second die, which may further increase the effectiveness of performing rework or repair on the stacked semiconductor device.

Abstract: A circuit, for a touch panel, comprises a plurality of touch signal processing circuits, coupled to a plurality of sensors of the touch panel to receive a plurality of touch signals, wherein when a first sensor within the plurality of sensors is touched, the first sensor generates a first touch signal of the plurality of touch signals; and a controller, coupled to the plurality of touch signal processing circuits, configured to adjust the first touch signal according to the plurality of touch signals except the first touch signal.

Abstract: Methods for forming a gate structure of a multi-gate device are provided. An example method includes depositing a gate dielectric layer over first nanostructures over a first region of a substrate and second nanostructures over a second region of the substrate, depositing a first work function metal (WFM) layer over the first nanostructures and the second nanostructures, depositing a first hard mask (HM) layer over the first WFM layer, selectively removing the first HM layer and the first WFM layer over the first region, selectively removing the first HM layer over the second region, depositing a second WFM layer over the substrate, depositing a second HM layer over the second WFM layer, selectively removing the second HM layer and the second WFM layer over the first region, selectively removing the second HM layer over the second region, and depositing a third WFM layer over the substrate.

Abstract: A die includes: a semiconductor substrate having a front side and an opposing back side; a dielectric structure including a substrate oxide layer disposed on the front side of the semiconductor substrate and interlayer dielectric (ILD) layers disposed on the substrate oxide layer; an interconnect structure disposed in the dielectric structure; a through-silicon via (TSV) structure extending in a vertical direction from the back side of the semiconductor substrate through the front side of the semiconductor substrate, such that a first end of the TSV structure is disposed in the interconnect structure; and a TSV barrier structure including a barrier line that contacts the first end of the TSV structure, and a first seal ring disposed in the substrate oxide layer and that surrounds the TSV structure in a lateral direction perpendicular to the vertical direction.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in a group of cut patterns which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.