Abstract: A method according to the present disclosure includes receiving a workpiece including a gate structure, a first source/drain (S/D) feature, a second S/D feature, a first dielectric layer over the gate structure, the first S/D feature, the second S/D feature, a first S/D contact over the first S/D feature, a second S/D contact over the second S/D feature, a first etch stop layer (ESL) over the first dielectric layer, and a second dielectric layer over the first ESL, forming a S/D contact via through the second dielectric layer and the first ESL to couple to the first S/D contact, forming a gate contact opening through the second dielectric layer, the first ESL, and the first dielectric layer to expose the gate structure, and forming a common rail opening adjoining the gate contact opening to expose the second S/D contact, and forming a common rail contact in the common rail opening.

Abstract: Semiconductor devices and methods of forming the same are provided. In an embodiment, a semiconductor device includes a first fin extending along a first direction, a second fin extending parallel to the first fin, and a gate structure over and wrapping around the first fin and the second fin, the gate structure extending along a second direction perpendicular to the first direction. The first fin bents away from the second fin along the second direction and the second fin bents away from the first fin along the second direction.

Abstract: Disclosed is a dual-frequency antenna including a dielectric carrier plate, a first radiator, a second radiator, a coupling radiator and a coaxial cable. The first radiator, the second radiator and the coupling radiator are disposed on a first surface of the dielectric carrier plate, and the coupling radiator is located between the first radiator and the second radiator and is spaced apart from the first radiator and the second radiator respectively. The coaxial cable includes an inner conductor, a first insulating layer covering part of the inner conductor, an outer conductor covering part of the first insulating layer, and a second insulating layer covering part of the outer conductor. The exposed inner conductor is electrically connected to the first radiator. The exposed outer conductor is electrically connected to the second radiator. Therefore, the dual-frequency antenna generates a first resonance mode and a second resonance mode with different center frequencies.

Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

Abstract: A three-dimensional device structure includes a die including a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, a through silicon via (TSV) structure that extends through the semiconductor substrate and electrically contacts a metal feature of the interconnect structure, and an integrated passive device (IPD) embedded in the semiconductor substrate and electrically connected to the TSV structure.

Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Abstract: A semiconductor device includes a first semiconductor die. The semiconductor device includes a redistribution structure disposed over a first side of the first semiconductor die and comprising a plurality of layers. At least a first one of the plurality of layers comprises a first power/ground plane embedded in a dielectric material and configured to provide a first supply voltage for the first semiconductor die. The first power/ground plane encloses a plurality of first conductive structures that are each operatively coupled to the first semiconductor die, and a plurality of second conductive structures scattered around the plurality of first conductive structures.

Abstract: An over-current protection device includes an electrode layer and a heat-sensitive layer. The heat-sensitive layer contacts a top metal layer and a bottom metal layer of the electrode layer, and is laminated therebetween. In addition, the heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a polymer matrix and a conductive filler. The polymer matrix includes a first fluoropolymer, by which the over-current protection device has a starting jump temperature of resistance ranging from 184° C. to 192° C. The conductive filler includes carbon black and a metal compound, thereby forming an electrically conductive path in the heat-sensitive layer.

Abstract: Depositing a side slab structure on a cladding layer before etching a supporting dielectric prevents tapering of a silicon waveguide during etching of the supporting dielectric and a substrate. For example, the side slab structure may be deposited over the silicon waveguide and the cladding layer after etching the cladding layer. As a result, when an electronic device is integrated ex situ on the substrate, wave intensity and/or total internal reflection is improved, which improves an efficiency of the electronic device.

Abstract: A method of fabricating a semiconductor device is described. A substrate is provided. Multiple fins are formed extending from the substrate, the fins including a first group of active fins in an active region and an inactive fin having at least a portion in an inactive region, the active fins separated by first trench regions, the inactive fin separated from its closest active fin by a second trench region, and the second trench region having a greater width than that of a trench region of the first trench regions. A dummy fin is formed on the isolation dielectric in the second trench region, the dummy fin disposed between the first group of active fins and the inactive fin. A dummy gate is formed over the fins. The gate isolation structure is disposed between the dummy fin and the inactive fin and separates regions of the dummy gate.

Abstract: An over-current protection device includes an electrode layer and a heat-sensitive layer. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic, and is laminated between a top metal layer and a bottom metal layer of the electrode layer. The heat-sensitive layer includes a polymer matrix and a conductive filler. The polymer matrix includes a fluorine-containing copolymer, and its melting point ranges from 210° C. to 240° C. The conductive filler consists of carbon black solely, and is used to form an electrically conductive path in the heat-sensitive layer. In addition, the over-current protection device has a resistance-jump ratio ranging from 1.2 to 1.3 between 40° C. and 130° C.

Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.

Abstract: A semiconductor device includes a first semiconductor die that operates at a first power, a second semiconductor die that is formed in a stack on the first semiconductor die and operates at a second power different than the first power, and a power management semiconductor die that is formed in the stack and provides the first power to the first semiconductor die through a first via and provides the second power to the second semiconductor die through a second via.

Abstract: A semiconductor package includes a first die; a second die stacked on the first die in a vertical direction; a dielectric encapsulation (DE) structure surrounding the first die and the second die in a lateral direction perpendicular to the vertical direction; and a package seal ring that extends through the DE structure and surrounds the second die and at least a portion of the first die, in the lateral direction.

Abstract: A mountable bracket includes a first leg and a second leg configured to be coupled to a mounting surface, a first sub-leg coupled to the first leg, and a second sub-leg coupled to the second leg. The first leg projects from the mounting surface to define a first engagement surface. The first sub-leg projects from the first leg to define a second engagement surface. The second leg projects from the mounting surface to define a third engagement surface. The second sub-leg projects from the second leg to define a fourth engagement surface. The second engagement surface and the first engagement surface form a first mounting rail having a first rail width. The fourth engagement surface and the third engagement surface form a second mounting rail having the first rail width. The first engagement surface and the third engagement surface form a third mounting rail having a second rail width.

Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: The present disclosure provides an immersion cooling system for a server cabinet including a plurality of server boxes, a cooling tank and a plurality of liquid connecting pipes. Each server box includes an electronic device immersed in the cooling liquid, and the electronic device generates a thermal energy so that part of the cooling liquid evaporates into a hot vapor. The cooling tank is connected to the plurality of server boxes and includes a condenser and a storage part. The condenser is connected to each server box and condenses the hot vapor to form the cooling liquid. The storage part storages the cooling liquid from the condenser. Two ends of the liquid connecting pipe is connected to the storage part and the server box respectively. The cooling liquid in the storage part and the cooling liquid of each server box are maintained in a same liquid level.

Abstract: A method of forming a semiconductor structure including a thermoelectric module embedded in the semiconductor substrate, where the thermoelectric module includes a first semiconductor structure electrically connected to a second semiconductor structure, where a bottom portion of thermoelectric module extends through a thickness of the semiconductor substrate, and where the first semiconductor structure and the second semiconductor structure include dopants of different conductivity types.

Abstract: Some implementations described herein provide an electronic device. The electronic device includes a first conductive structure that extends through a dielectric structure of the electronic device and into a substrate of the electronic device. The electronic device includes a guard ring, having multiple layers, that extends along one or more sides of a first vertical portion of the first conductive structure. The electronic device includes a second conductive structure that extends along a second vertical portion of the first conductive structure, where the second conductive structure includes a conductive structure side surface, which is nearest to a side surface of the first conductive structure, that is a distance from the side surface of the first conductive structure, and where the distance is greater than or equal to approximately 5% of a width of the first conductive structure.

Abstract: A semiconductor device includes an inductance structure and a shielding structure. The shielding structure is arranged to at least partially shield the inductance structure from external electromagnetic fields. The shielding structure includes a shielding structure portion arranged along a side of the inductance structure such that the shielding structure portion is around at least a portion of a perimeter of the inductance structure.