Abstract: A memory device includes a memory cell array including memory cells; a page buffer circuit including a plurality of page buffers coupled to the memory cell array, each page buffer including a plurality of latches and an internal data line (IDL) arranged to couple to the plurality of latches; and a cache circuit including a plurality of caches. The IDLs of the plurality of page buffers are configured to be conductively connected together to form a data bus (DBUS) that conductively connects the page buffer circuit to the cache circuit for data transfer.

Abstract: An integrated semiconductor packaging system includes: a first wet clean tool configured to perform a first wet clean process on a frame, wherein a plurality of top dies are disposed on the frame; a second wet clean tool configured to perform a second wet clean process on a wafer, wherein a plurality of bottom dies corresponding to the plurality of top dies, respectively, are disposed on the wafer; a pick-and-place tool configured to bond the plurality of top dies to the plurality of bottom dies, respectively; and a first transmission path through which the frame and the wafer are transferred from the first wet clean tool and the second wet clean tool to the pick-and-place tool, respectively, wherein the frame is directly transferred from the first wet clean tool to the pick-and-place tool, and the wafer is directly transferred from the second wet clean tool to the pick-and-place tool.

Abstract: In an embodiment, a device includes: a first gate dielectric on a first channel region of a first semiconductor feature; a first gate electrode on the first gate dielectric; a second gate dielectric on a second channel region of a second semiconductor feature, the second gate dielectric having a greater crystallinity than the first gate dielectric; and a second gate electrode on the second gate dielectric.

Abstract: A method of making a semiconductor device includes manufacturing an ESD cell over a substrate, wherein the ESD cell includes multiple diodes connected in parallel to each other. The method includes manufacturing a conductive pillar electrically connected to the ESD cell of the semiconductor device; manufacturing a through-silicon via (TSV) extending through the substrate, wherein the TSV extends through the substrate within a TSV zone having a TSV zone perimeter, and wherein a first end of the TSV is at a same side of the substrate as the ESD cell, and a second end of the TSV is at a different side of the substrate from the ESD cell. The method includes manufacturing an antenna extending parallel to the TSV at a same side of the substrate as the ESD cell; and manufacturing an antenna pad electrically connected to the TSV, the antenna, and the conductive pillar.

Abstract: A three-dimensional device structure includes a die including a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, a through silicon via (TSV) structure that extends through the semiconductor substrate and electrically contacts a metal feature of the interconnect structure, and an integrated passive device (IPD) embedded in the semiconductor substrate and electrically connected to the TSV structure.

Abstract: A backlight module includes a light source, a first prism sheet disposed on the light source, and a light type adjustment sheet disposed on a side of the first prism sheet away from the light source and including a base and multiple light type adjustment structures. The multiple light type adjustment structures are disposed on the first surface of the base. Each light type adjustment structure has a first structure surface and a second structure surface connected to each other. The first structure surface of each light type adjustment structure and the first surface of the base form a first base angle therebetween, and the second structure surface of each light type adjustment structure and the first surface of the base form a second base angle therebetween. The angle of the first base angle is different from the angle of the second base angle.

Abstract: Embodiments of the present disclosure provide a semiconductor device with backside source/drain contacts formed using a buried source/drain feature and a semiconductor cap layer formed between the buried source/drain feature and a source/drain region. The buried source/drain feature and the semiconductor cap layer enable self-aligned backside source/drain contact and backside isolation. The semiconductor cap layer functions as an etch stop layer during backside contact formation while enabling source/drain region growth without fabrication penalty, such as voids in the source/drain regions.

Abstract: A glass composition includes, based on 100 wt % of the glass composition, silicon dioxide present in an amount ranging from 45 wt % to 61 wt %, aluminum oxide present in an amount (A) ranging from 15 wt % to 22 wt %, calcium oxide present in an amount (C) ranging from 0.1 wt % to 6 wt %, magnesium oxide present in an amount (M) of greater than 0 wt % and lower than 2 wt %, zinc oxide present in an amount of greater than 0 wt % and lower than 8 wt %, copper oxide present in an amount of greater than 0 wt % and lower than 7 wt %, and boron oxide present in an amount of greater than 6 wt % and lower than 18 wt %. A glass fiber including the glass composition, and an electronic product including the glass fiber are also provided.

Abstract: A deep learning method of an artificial intelligence model for medical image recognition is provided. The method includes the following steps: obtaining a first image set, where the first image set includes at least two images captured with different parameters; performing image pre-processing on each image of the first image set to obtain a second image set; performing image augmentation on the second image set to obtain a third image set; adding the third image set to a training image data set; and training the artificial intelligence model using the training image data set.

Abstract: A power supply includes a conversion circuit, an auxiliary power circuit, and an output control circuit. The conversion circuit converts a DC power into a first output power, and the auxiliary power circuit converts the DC power into a first auxiliary power. The output control circuit is used to selectively connect a first output terminal and a second output terminal so that when the output control circuit disconnects the first output terminal and the second output terminal, the first output power supplies power to a critical load through the first output terminal, and when the output control circuit connects the first output terminal and the second output terminal, the first output power supplies power to the critical load and a non-critical load through the first output terminal and the second output terminal respectively.

Abstract: A method of fabricating a semiconductor package includes: providing a first die group including a plurality of first dies stacked parallel to a front surface of the first die group; providing a second die group including a plurality of second dies parallel to a front surface of the second die group; providing a base substrate structure comprising a substrate characterized by a lattice crystalline plane extending in a third direction; bonding the first die group on the base substrate structure, wherein the first edge extends in a first direction, and the first direction and the third direction define a first angle; and bonding the second die group on the base substrate structure, wherein the second edge extends in a second direction, and the second direction and the third direction define a second angle, and at least one of the first angle and the second angle is not zero.

Abstract: Boundary cells may be provided. A boundary of a first functional cell of a circuit is determined. A first plurality of a first type of dummy cells are placed along a first portion of the determined boundary. The first portion extends in a first direction. Each of the first type of dummy cells comprises first pre-defined dimensions. A second plurality of a second type of dummy cells are placed along a second portion of the determined boundary. The second portion extends in a second direction. Each of the second type of dummy cells comprises second pre-defined dimensions. The second pre-defined dimensions is different than the first pre-defined dimensions.

Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

Abstract: A method includes forming a dummy component, including: forming through-substrate vias (TSVs) in a substrate; forming a thermal structure over the TSVs, wherein the thermal structure includes metal lines in dielectric layers; forming a bonding layer over the thermal structure; and forming bond pads within the bonding layer; bonding the dummy component to a package component; and bonding a semiconductor die to the package component.

Abstract: An antenna system includes: a first group of MIMO antennas including a first dual-band antenna arranged at first corner of the base, a second dual-band antenna arranged on a first side of the base, a first single band antenna arranged at a second corner of the base, a second single band antenna parallel to the base; a second group of MIMO antennas including a third single band antenna vertically arranged in a third corner of the base, a fourth single band antenna arranged at a fourth corner of the base, a fifth single band antenna in planar structure, a sixth single band antenna arranged between the first single band antenna and the third single band antenna; a first isolation component arranged between the second dual-band antenna and the fifth single band antenna; a second isolation component arranged between the second single band antenna and the sixth single band antenna.

Abstract: The disclosure provides an apparatus for substrate polishing, the apparatus includes a housing member, a carrier member, and a distal force assembly. The carrier member is coupled to and disposed radially outward of the housing member. The distal force assembly disposed radially inward of an exterior portion of the carrier member and radially outward of the housing member. The distal force assembly includes a bladder seal, a seal ring in contact with the bladder seal. The seal ring has a seal ring face and one or more grooves disposed therein. The grooves include a plateau radius and a ridge radius disposed opposite the plateau radius at an intersection between the seal ring face and the grooves, wherein the plateau radius and the ridge radius are between about 0.012 to about 0.018 inches. The distal force assembly also includes a transfer ring coupled to the seal ring opposite the bladder.

Abstract: Depositing a side slab structure on a cladding layer before etching a supporting dielectric prevents tapering of a silicon waveguide during etching of the supporting dielectric and a substrate. For example, the side slab structure may be deposited over the silicon waveguide and the cladding layer after etching the cladding layer. As a result, when an electronic device is integrated ex situ on the substrate, wave intensity and/or total internal reflection is improved, which improves an efficiency of the electronic device.

Abstract: A multiply accumulate circuit receives m one-bit neuron values from a first layer of a neural network system. The multiply accumulate circuit includes m non-volatile memory cells and m current sources. In addition, m current paths are defined by the m non-volatile memory cells and the m current sources collaboratively. A first current path is defined by a first non-volatile memory cell and a first current source. A first terminal of the first current source receives a first supply voltage. A second terminal of the first current source is connected with a first terminal of the first non-volatile memory cell. A second terminal of the first non-volatile memory cell is connected with an output terminal of the multiply accumulate circuit. A control terminal of the first current source receives a first one-bit neuron value.

Abstract: Packaged semiconductor devices including high-thermal conductivity molding compounds and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution structure; a first die over and electrically coupled to the first redistribution structure; a first through via over and electrically coupled to the first redistribution structure; an insulation layer extending along the first redistribution structure, the first die, and the first through via; and an encapsulant over the insulation layer, the encapsulant surrounding portions of the first through via and the first die, the encapsulant including conductive fillers at a concentration ranging from 70% to about 95% by volume.

Abstract: A fabricating method of a high electron mobility transistor includes providing a substrate. Then, a channel layer, an active layer, a P-type group III-V compound material layer, a metal compound material layer, a hard mask material layer and a patterned photoresist are formed to cover the substrate. Later, a dry etching process is performed to etch the hard mask material layer and the metal compound material layer to form a hard mask and a metal compound layer by taking the patterned photoresist as a mask. During the dry etching process, a spacer generated by by-products is formed to surround the patterned photoresist, the hard mask and the metal compound layer. After the dry etching process, the P-type group III-V compound material layer is etched by taking the spacer and the patterned photoresist as a mask.