Abstract: A filler cell, a semiconductor device, and a logic circuit are provided. The filler cell includes two dummy polysilicon layers and a threshold voltage layer. The dummy polysilicon layers are arranged at intervals in a first direction. The threshold voltage layer is below the dummy polysilicon layers, and the two opposite sides of the threshold voltage layer in the first direction extend in a second direction and are respectively aligned with center points of the dummy polysilicon layers. The two opposite sides of the threshold voltage layer in the second direction are respectively aligned with the two opposite sides of each of the dummy polysilicon layers in the second direction. The first direction is perpendicular to the second direction. The semiconductor device includes a plurality of filler cells, at least one transistor cell, and another two threshold voltage layers. The logic circuit includes a plurality of semiconductor devices.

Abstract: A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device comprises a substrate, a conductive element disposed within a first region of the substrate, and a first transistor disposed within a second region adjacent to the first region of the substrate. The conductive element is electrically connected to an electrode of the first transistor, and the conductive element penetrates the substrate and is configured to receive a supply voltage.

Abstract: A display device includes a back plate, a display panel, an elastic layer, a light guide plate, a cover plate and an adhesive layer. The display panel is opposite to an installing surface of the back plate. The elastic layer is compressed between the back plate and the display panel. The light guide plate is between the elastic layer and the adhesive layer. The adhesive layer is between the light guide plate and the cover plate, and includes a main body portion and an edge reinforcing portion surrounding the main body portion and connected to the light guide plate and the cover plate. The main body portion includes a first adhesive body disposed on the light guide plate and a second adhesive body stacked on the first adhesive body and the cover plate. An adhesion of the first adhesive body is different from an adhesion of the second adhesive body.

Abstract: Provided is a method for treating a SARS-CoV2 3CLpro-related disease in a subject in need thereof by blocking dimerization of 3C-like main protease (3CLpro) of the SARS-CoV2, including administering to the subject a first agent which binds to a first binding site of a SARS-CoV2 3CLpro complex and a second agent which binds to a second binding site of the SARS-CoV2 3CLpro complex, wherein the first binding site and the second binding site are functionally different sites in the three-dimensional structure of the SARS-CoV2 3CLpro complex. Also provided is a pharmaceutical combination including the first agent and the second agent for suppressing SARS-CoV2, thereby alleviating COVID-19.

Abstract: A dosing system and method for delivery of contact lens formulation(s) to a contact lens forming mold. The system includes a carrier portion configured for holding a contact lens mold, and an alignment mandrel configured for retaining a lens formulation delivery device. The lens formulation delivery device is retained in a specified position relative to the contact lens mold for precise location of delivery of the lens formulation within the contact lens mold. A first lens formulation can be dosed to a center location in the mold, and a different second lens formulation can be dosed to a ring-shaped pattern around the center location, to form a contact lens having different center and edge characteristics.

Abstract: An optical element driving mechanism is provided, which includes a first movable portion, a fixed portion, a first driving assembly, and a guiding assembly. The first movable portion is used for connecting to an optical element. The first movable portion is movable relative to the fixed portion. The first driving assembly is used for driving the first movable portion to move relative to the fixed portion. The guiding assembly is used for guiding the first movable portion to move relative to the fixed portion.

Abstract: A method includes providing a substrate having an epitaxial stack of layers including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. The substrate includes a first device region and a second device region. An etch process is performed to remove a first portion of the epitaxial stack of layers from the second device region to form a trench in the second device region. The removed first portion of the epitaxial stack of layers includes at least one semiconductor channel layer of the plurality of semiconductor channel layers. An epitaxial layer is formed within the trench in the second device region and over the second portion of the epitaxial stack of layers. A top surface of the epitaxial layer in the second device region is substantially level with a top surface of the epitaxial stack of layers in the first device region.

Abstract: A method includes: receiving a layout of an integrated circuit; identifying, based on the layout, at least a first net and at least a second net, wherein the first net extends through the integrated circuit along a vertical direction, and the second net terminates at a middle portion of the integrated circuit along the vertical direction; dividing the integrated circuit into a plurality of grid units, wherein he first net is constituted by a first subset of the plurality of grid units, and the second net is constituted by a second subset of the plurality of grid units; estimating a first thermal conductivity of each of the first subsets of grid units; estimating a second thermal conductivity of each of the second subsets of grid units; and estimating an equivalent thermal conductivity of the integrated circuit based on combining the first thermal conductivity and the second thermal conductivity.

Abstract: A driving mechanism for moving an optical element is provided. The driving mechanism includes a fixed part, a movable part, and a driving assembly. The movable part is movably connected to the fixed part for holding the optical element. The driving assembly is configured for moving the movable part relative to the fixed part.

Abstract: Systems, devices, and methods are disclosed for fabricating a hybrid contact lens product having a lens insert embedded at a precisely controlled location within a lens body. A mold engagement and support base engages and retains a lens forming mold in a substantially fixed position. An insert placement and positioning device includes an insert pickup head with a contact face configured for releasable engagement of the lens insert and at least one suction opening in the contact face for applying suction to engage the insert on the contact face. A positioning housing interacts with the mold and/or the support base to provide precise locational positioning of the lens insert within the mold. A lens body forming material is delivered to the mold to encapsulate the lens insert.

Abstract: A die stack includes: a first die including a first semiconductor substrate; a first redistribution layer (RDL) structure disposed on a front surface of the first die and electrically connected to the first semiconductor substrate; a second die bonded to the front surface of the first die and including a second semiconductor substrate; a third die bonded to the front surface of the first die and including a third semiconductor substrate; a second RDL structure disposed on front surfaces of the second and third dies and electrically connected to the second and third semiconductor substrates; and a through dielectric via (TDV) structure extending between the second and third dies and electrically connected to the first RDL structure and second RDL structure. The second and third dies are disposed in a plane that extends perpendicular to a vertical stacking direction of the die stack.

Abstract: Devices and methods for manufacturing a deep trench capacitor fuse for high voltage breakdown defense. A semiconductor device comprising a deep trench capacitor structure and a transistor structure. The transistor structure may comprise a base, a first terminal formed within the base, and a second terminal formed within the base. The first terminal and the second terminal may be formed by doping the base. The deep trench capacitor structure may comprise a first metallic electrode layer and a second metallic electrode layer. The first terminal may be electrically connected to the first metallic electrode layer, and the second terminal may be electrically connected to the second metallic electrode layer.

Abstract: The invention is directed to an embedded hydrogel contact lens, which comprises an insert sandwiched between two layers of hydrogel materials and can be produced according to a cast molding method including the procedures involving two females halves (FC1 and FC2) and two male halves (BC1 and BC2) and three consequential molding steps involving three molding assemblies: the 1st one formed between FC1 and BC1 for molding an insert; the 2nd one formed between FC1 and BC2 for molding a lens precursor having the molded insert embedded in a layer of a hydrogel material in a way that the front surface of the molded insert merges with the convex surface of the lens precursor; and the 3rd one formed between FC2 and BC2 for molding an embedded hydrogel contact of the invention.

Abstract: A method for establishing an artificial intelligence prediction model that integrates with a large language model (LLM) in the field of artificial intelligence is provided. The method for establishing the artificial intelligence prediction model includes the creation of the prediction model, obtaining predictions using the model, interpreting the results using SHAP analysis, and leveraging a large language model to overcome the format limitations encountered when dealing with input and output data. A system of an artificial intelligence prediction model is also provided.

Abstract: An electronic device and a power supply optimization method thereof are provided. The method includes: negotiating with a power adapter through a power control protocol in a power connection state to obtain a power profile; determining whether the power adapter supports a variable charging power adjustment function according to the power profile; when the power adapter supports the variable charging power adjustment function, determining whether a stored power of a battery module is less than a power threshold; when the stored power is less than the power threshold, executing one or more of a constant current test, a constant voltage test, and a power transmission test to select an algorithm for controlling a power supply behavior of the power adapter from multiple algorithms.

Abstract: An adhesive and multilayer structure are provided. The adhesive includes a polyimide, wherein the polyimide is a reaction product of a reactant (a) and a reactant (b). The reactant (a) is a first diamine or the reactant (a) includes of a first diamine and a second diamine, and the reactant (b) includes of a first dianhydride and a second dianhydride. The first diamine is a diphenyl-ether-moiety-containing diamine, the first dianhydride is a diphenyl-ether-moiety-containing dianhydride, the second diamine is not a diphenyl-ether-moiety-containing diamine, and the second dianhydride is not a diphenyl-ether-moiety-containing dianhydride. The total weight percentage of the first diamine and the first dianhydride is 55 wt % to 94 wt %, based on the total weight of the reactant (a) and the reactant (b).

Abstract: Disclosed is a dual-band dipole antenna including a dielectric carrier with a first surface, a first radiator, a second radiator, a coupled radiator, a coaxial cable and a balun line. The first radiator and the second radiator in opposite areas of the first surface have different structural shapes. The coupled radiator on the first surface extends from the second radiator toward the first radiator. There is a coupling slot between the coupled radiator and the first radiator. An inner conductor and an outer conductor of the coaxial cable are electrically connected to the second radiator and the first radiator respectively. The balun line disposed on the first surface has a serpentine structure, and is connected to the first radiator and the second radiator. The first radiator, the second radiator and the coupled radiator are configured to generate a first resonance mode, a second resonance mode and a third resonance mode.

Abstract: A control circuit is included in a first die of a stacked semiconductor device. The first die further includes a transistor that is electrically connected to the control circuit. The transistor is configured to be controlled by the control circuit to selectively block a die-to-die interconnect. In this way, the die-to-die interconnect may be selectively blocked to isolate the first die and a second die of the stacked semiconductor device for independent testing after bonding. This may increase the effectiveness of a testing to identify and isolate defects in the first die or the second die, which may further increase the effectiveness of performing rework or repair on the stacked semiconductor device.

Abstract: The present disclosure describes a memory structure including a memory cell array. The memory cell array includes memory cells and first n-type wells extending in a first direction. The memory structure also includes a second n-type well formed in a peripheral region of the memory structure. The second n-type well extends in a second direction and is in contact with a first n-type well of the first n-type wells. The memory structure further includes a pick-up region formed in the second n-type well. The pick-up region is electrically coupled to the first n-type well of first n-type wells.

Abstract: A device includes a substrate, at least one first dielectric layer on the substrate and including a first dielectric constant, at least one second dielectric layer on the at least one first dielectric layer and including a second dielectric constant greater than the first dielectric constant, and a dummy pattern including a first conductive pattern having a first pattern density in the at least one first dielectric layer and a second conductive pattern in the at least one second dielectric layer and comprising a second pattern density. The first pattern density is equal to or greater than the second pattern density.