Abstract: A thermoplastic polyurethane precursor that can be used to prepare a polyurethane having a low initial yellowness index, high yellowing resistance, high thermal oxidative aging resistance, high hydrolysis resistance, and low fisheye.

Abstract: An electronic device and an image processing method thereof are provided. The image processing method includes the following steps: detecting whether a buffer has second image data when performing a first compositing operation of first image data; detecting whether an image capturing operation of third image data is performed; judging a first time point for obtaining the third image data; and comparing a second time point for completing the first compositing operation to the first time point and determining whether to perform a second compositing operation of the second image data first or a third compositing operation of the third image data first.

Abstract: A manufacturing method of a semiconductor package includes the following steps. A first lower semiconductor device and a second lower semiconductor device are provided. A plurality of first conductive pillars are formed on the first lower semiconductor device along a first direction parallel to a side of the first lower semiconductor device. A plurality of second conductive pillars are formed on the second lower semiconductor device along a second direction parallel to a side of the second lower semiconductor device, wherein the first direction is substantially collinear with the second direction. An upper semiconductor device is disposed on the first lower semiconductor device and the second lower semiconductor device and revealing a portion where the plurality of first conductive pillars and the plurality of second conductive pillars are disposed.

Abstract: An over-current protection device includes an electrode layer and a heat-sensitive layer. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic, and is laminated between a top metal layer and a bottom metal layer of the electrode layer. The heat-sensitive layer includes a polymer matrix and a conductive filler. The polymer matrix includes a fluoropolymer. The fluoropolymer has a plurality of spherulites, and the fractal dimension of each spherulite is lower than 12.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a substrate; depositing a mask layer over the substrate; forming a mandrel pattern over the mask layer; forming a spacer pattern around the mandrel pattern; removing the mandrel pattern; and applying at least one directional etching operation along a first direction to etch two opposing ends of the spacer pattern and form a first spacer feature and a second spacer feature apart from each other.

Abstract: In a method for inspecting pattern defects, a plurality of patterns are formed over an underlying layer. The plurality of patterns are electrically isolated from each other. A part of the plurality of patterns are scanned with an electron beam to charge the plurality of patterns. An intensity of secondary electrons emitted from the scanned part of the plurality of patterns is obtained. One or more of the plurality of patterns that show an intensity of the secondary electrons different from others of the plurality of patterns are searched.

Abstract: A test key configured to measure resistance of a through semiconductor via in a semiconductor substrate is provided. The test key includes a first resistor, a first conductor, a first probe pad, a second conductor, a second probe pad, a third conductor, a third probe pad, a fourth conductor, and a fourth probe pad. The first probe pad is electrically connected to a first end of the through semiconductor via by the first resistor and the first conductor. The second probe pad is electrically connected to the first end of the through semiconductor via by the second conductor. The third probe pad is electrically connected to a second end of the through semiconductor via by the third conductor. The fourth probe pad is electrically connected to the second end of the through semiconductor via by the fourth conductor.

Abstract: A memory device includes a first layer, wherein the first layer includes a first memory array, a first row decoder circuit, and a first column sensing circuit. The memory device includes a second layer disposed with respect to the first layer in a vertical direction. The second layer includes a first peripheral circuit operatively coupled to the first memory array, the first row decoder circuit, and the first column sensing circuit. The memory device includes a plurality of interconnect structures extending along the vertical direction. At least a first one of the plurality of interconnect structures operatively couples the second layer to the first layer.

Abstract: A method of forming a package device includes providing a carrier substrate, forming a trench in a front side of the carrier substrate, and bonding a semiconductor die in the trench. The method also includes thinning a back side of the carrier substrate based on a target thickness to obtain a thinned carrier substrate. The method further includes providing a first die group and bonding the thinned carrier substrate to the first die group to form a height-adjusted first die group.

Abstract: A digital compute-in-memory (DCIM) macro includes a memory cell array and an arithmetic logic unit (ALU). The memory cell array stores weight data of a neural network. The ALU receives parallel bits of a same input channel in an activation input, and generates a convolution computation output of the parallel bits and target weight data in the memory cell array.

Abstract: A digital compute-in-memory (DCIM) system includes a first DCIM macro. The first DCIM macro includes a first memory cell array and a first arithmetic logic unit (ALU). The first memory cell array has N rows that are configured to store weight data of a neural network in a single weight data download session, wherein N is a positive integer not smaller than two. The first ALU is configured to receive a first activation input, and perform convolution operations upon the first activation input and a single row of weight data selected from the N rows of the first memory cell array to generate first convolution outputs.

Abstract: A memory device includes a plurality of circuit layers, a plurality of first conductive through via structures and a plurality of bitlines. The circuit layers are disposed one above another, and each circuit layer includes one or more memory cell arrays. The first conductive through via structures penetrates though the circuit layers. Each of the bitlines includes a plurality of bitline segments disposed on the circuit layers respectively. The bitline segments are electrically connected through one of the first conductive through via structures. Each bitline segment is coupled to a plurality of memory cells of a memory cell array of a circuit layer where the bitline segment is disposed.

Abstract: A semiconductor device comprises: a silicon carbide epitaxial layer. The silicon carbide epitaxial layer has: a p-type buried layer; and a junction field effect region in contact with the p-type buried layer in a gate region. The semiconductor device further comprises: a gate oxide layer on the silicon carbide epitaxial layer; a poly silicon layer on the gate oxide layer; an interlayer dielectric layer on the poly silicon layer; a first recess formed in the silicon carbide epitaxial layer by passing through the interlayer dielectric layer, the poly silicon layer and the gate oxide layer in a source region; and a second recess formed in the poly silicon layer in the gate region, wherein a bottom surface of the second recess is higher than a top surface of the gate oxide layer.

Abstract: A stress modulating device including a semiconductor substrate, a first insulating layer formed over a first side of the semiconductor substrate, a second insulating layer formed over the first insulating layer, a third insulating layer formed over a second side of the semiconductor substrate, a fourth insulating layer formed over the third insulating layer, and a fifth insulating layer formed over the fourth insulating layer for incorporation in multi-stack package assemblies for reducing stress, strain, and/or warpage on the active elements within the package assembly.

Abstract: A method includes forming an integrated circuit and a testing pattern over a die region of a wafer and a scribe line region of the wafer, respectively, in which the integrated circuit and the testing pattern are formed by a same fabrication process; connecting a via of a testing chip to a testing pad of the testing pattern; performing a testing process to the die region by detecting electrical properties of the testing pattern through the testing chip; after the testing process is completed, forming an interconnection structure over the integrated circuit, in which the interconnection structure includes conductive features electrically connected to the integrated circuit; and after the interconnection structure is formed over the integrated circuit performing an singulation process through the scribe line region of the wafer, such that the die region of the wafer is singulated into an individual die.

Abstract: Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.

Abstract: A package structure and method of manufacturing a package structure are provided. The package structure includes two semiconductor structures and two bonding layers sandwiched between both semiconductor structures. Each bonding layer has a plurality of bonding pads separated by an isolation layer. Each bonding pad has a bonding surface including a bonding region and at least one buffer region. The bonding regions in both bonding layers bond to each other. The buffer region of one semiconductor structure bonds to the isolation layer of the other semiconductor structure. Each first bonding pad has a front cross-section with a length greater than a length of a front cross-section of each second bonding pads; and each second bonding pads has a side cross-section with a length greater than a length of a front cross-section of each first bonding pad.

Abstract: A semiconductor package includes: a base substrate structure; and a plurality of die groups disposed on a top surface of the based substrate structure, the plurality of die groups comprising a first die group and a second die group neighboring to each other. The first die group includes a plurality of first dies stacked parallel to each other and parallel to a front surface of the first die group, the front surface of the first die group and the top surface intersect at a first edge extending in a first direction. The second die group includes a plurality of second dies stacked parallel to each other and parallel to a front surface of the second die group, the front surface of the second die group and the top surface intersect at a second edge extending in a second direction not parallel to the first direction.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a first substrate. The first substrate includes a first dielectric layer, and a vertical conductive area, where the vertical conductive area includes one or more vertical conductive structures extending through the first dielectric layer, where each line segment of a non-square quadrilateral contacts at least one of the one or more vertical conductive structures. The vertical conductive area also includes a continuous conductive guard ring structure in the first dielectric layer, where the continuous conductive guard ring structure surrounds the one or more vertical conductive structures. The semiconductor device also includes a second substrate, including a first conductor, and a second conductor, where the first conductor of the second substrate is electrically connected to at least one of the vertical conductive structures of the first substrate.