Abstract: A manufacturing method of an electronic package includes the following steps. A first interfacial dielectric layer is formed to cover sides of multiple first conductive vias and multiple second conductive vias. Multiple chips are directly bonded to the first and second conductive vias. A base dielectric layer is formed to fill a gap between the adjacent chips. A bridge element is directly bonded to the first conductive vias, such that the bridge element partially overlaps the adjacent chips respectively. A second interfacial dielectric layer and multiple third conductive vias are formed on the first interfacial dielectric layer and the bridge element. A redistribution circuit structure is formed on the second interfacial dielectric layer and the third conductive vias. Multiple conductive bumps are formed on the redistribution circuit structure. An electronic package is also provided.

Abstract: Provided is a light-emitting quantum dot coated with at least one blue-light absorption layer, including an alloy core consisting of Cd, Se, Zn, and S, at least one first shell layer which has a wurtzite structure and is coated on a surface of the alloy core; and a second shell layer consisting of ZnS and, having a zinc blende structure and is coated on a surface of the first shell layer, wherein the element ratio of each of Zn and S accounts for 30 to 50% of the overall core, and the content of Cd and Se gradually decreases outward from the core center. Also provided is a method for preparing the core-shell type light-emitting quantum dot.

Abstract: A front light module provided includes a light-emitting element, a light guide plate, and a film assembly. The light guide plate has a light-incident surface and a light-exiting surface. The light-incident surface is connected to the light-exiting surface and is disposed opposite to the light-emitting element. The light-exiting surface has a plurality of microstructures. The film assembly includes a first light-penetrating adhesive layer, an optical film, and a second light-penetrating adhesive layer. The first light-penetrating adhesive layer is connected to the light-exiting surface. The optical film is disposed between the first light-penetrating adhesive layer and the second light-penetrating adhesive layer, and the first light-penetrating adhesive layer is disposed between the light guide plate and the optical film. A display device having the front light module is also provided. The front light module and the display device can improve the visibility.

Abstract: An array of complementary die sets is attached to a carrier substrate. A continuous complementary-level molding compound layer is formed around the array of complementary die sets. An array of primary semiconductor dies is attached to the array of complementary die sets. A continuous primary-level molding compound layer is formed around the array of primary semiconductor dies. The bonded assembly is diced by cutting along directions that are parallel to edges of the primary semiconductor dies. The sidewalls of the complementary dies are azimuthally tilted relative to sidewalls of the primary semiconductor dies, or major crystallographic directions of a single crystalline material in the carrier substrate are azimuthally tilted relative to sidewalls of the primary semiconductor dies.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are disclosed. The semiconductor structure includes a first die including a fuse structure in a topmost layer of the first die, the fuse structure including a pair of conductive segments, wherein one of the pair of conductive segments is electrically connected to a bonding pad of the first die, wherein the bonding pad is electrically connected to ground; and an inductor electrically connected to the one of the pair of conductive segments.

Abstract: A control circuit is included in a first die of a stacked semiconductor device. The first die further includes a transistor that is electrically connected to the control circuit. The transistor is configured to be controlled by the control circuit to selectively block a die-to-die interconnect. In this way, the die-to-die interconnect may be selectively blocked to isolate the first die and a second die of the stacked semiconductor device for independent testing after bonding. This may increase the effectiveness of a testing to identify and isolate defects in the first die or the second die, which may further increase the effectiveness of performing rework or repair on the stacked semiconductor device.

Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in a group of cut patterns which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Abstract: A die includes: a semiconductor substrate having a front side and an opposing back side; a dielectric structure including a substrate oxide layer disposed on the front side of the semiconductor substrate and interlayer dielectric (ILD) layers disposed on the substrate oxide layer; an interconnect structure disposed in the dielectric structure; a through-silicon via (TSV) structure extending in a vertical direction from the back side of the semiconductor substrate through the front side of the semiconductor substrate, such that a first end of the TSV structure is disposed in the interconnect structure; and a TSV barrier structure including a barrier line that contacts the first end of the TSV structure, and a first seal ring disposed in the substrate oxide layer and that surrounds the TSV structure in a lateral direction perpendicular to the vertical direction.

Abstract: A method of making a semiconductor device includes manufacturing an ESD cell over a substrate, wherein the ESD cell includes multiple diodes connected in parallel to each other. The method includes manufacturing a conductive pillar electrically connected to the ESD cell of the semiconductor device; manufacturing a through-silicon via (TSV) extending through the substrate, wherein the TSV extends through the substrate within a TSV zone having a TSV zone perimeter, and wherein a first end of the TSV is at a same side of the substrate as the ESD cell, and a second end of the TSV is at a different side of the substrate from the ESD cell. The method includes manufacturing an antenna extending parallel to the TSV at a same side of the substrate as the ESD cell; and manufacturing an antenna pad electrically connected to the TSV, the antenna, and the conductive pillar.

Abstract: A measuring system and a measuring method of an antenna pattern based on near field to far field transformation (NFTF) are provided. The measuring system includes a probe antenna, a reference antenna, and a control system. The probe antenna measures an electric field radiated by an antenna under test to obtain electric field information. The reference antenna measures the electric field to obtain a reference phase. The control system is coupled to the antenna under test, the probe antenna, and the reference antenna, wherein the control system applies near field focusing to the reference antenna to configure a focus point of the reference antenna on the antenna under test, and the control system performs the NFTF according to the electric field information and the reference phase to output far field patterns.

Abstract: The invention is related to contact lenses that not only comprise the much desired water gradient structural configurations, but also have a minimized uptakes of polycationic antimicrobials and a long-lasting surface hydrophilicity and wettability even after going through a 30-days lens care regime. Because of the water gradient structural configuration and a relatively-thick, extremely-soft and water-rich hydrogel surface layer, a contact lens of the invention can provide superior wearing comfort. Further, a contact lens of the invention is compatible with multipurpose lens care solutions present in the market and can endure the harsh lens care handling conditions (e.g., digital rubbings, accidental inversion of contact lenses, etc.) encountered in a daily lens care regime. As such, they are suitable to be used as weekly- or monthly-disposable water gradient contact lenses.

Abstract: A memory device includes a memory cell array including memory cells; a page buffer circuit including a plurality of page buffers coupled to the memory cell array, each page buffer including a plurality of latches and an internal data line (IDL) arranged to couple to the plurality of latches; and a cache circuit including a plurality of caches. The IDLs of the plurality of page buffers are configured to be conductively connected together to form a data bus (DBUS) that conductively connects the page buffer circuit to the cache circuit for data transfer.

Abstract: An integrated semiconductor packaging system includes: a first wet clean tool configured to perform a first wet clean process on a frame, wherein a plurality of top dies are disposed on the frame; a second wet clean tool configured to perform a second wet clean process on a wafer, wherein a plurality of bottom dies corresponding to the plurality of top dies, respectively, are disposed on the wafer; a pick-and-place tool configured to bond the plurality of top dies to the plurality of bottom dies, respectively; and a first transmission path through which the frame and the wafer are transferred from the first wet clean tool and the second wet clean tool to the pick-and-place tool, respectively, wherein the frame is directly transferred from the first wet clean tool to the pick-and-place tool, and the wafer is directly transferred from the second wet clean tool to the pick-and-place tool.

Abstract: A three-dimensional device structure includes a die including a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, a through silicon via (TSV) structure that extends through the semiconductor substrate and electrically contacts a metal feature of the interconnect structure, and an integrated passive device (IPD) embedded in the semiconductor substrate and electrically connected to the TSV structure.

Abstract: A glass composition includes, based on 100 wt % of the glass composition, silicon dioxide present in an amount ranging from 45 wt % to 61 wt %, aluminum oxide present in an amount (A) ranging from 15 wt % to 22 wt %, calcium oxide present in an amount (C) ranging from 0.1 wt % to 6 wt %, magnesium oxide present in an amount (M) of greater than 0 wt % and lower than 2 wt %, zinc oxide present in an amount of greater than 0 wt % and lower than 8 wt %, copper oxide present in an amount of greater than 0 wt % and lower than 7 wt %, and boron oxide present in an amount of greater than 6 wt % and lower than 18 wt %. A glass fiber including the glass composition, and an electronic product including the glass fiber are also provided.

Abstract: A deep learning method of an artificial intelligence model for medical image recognition is provided. The method includes the following steps: obtaining a first image set, where the first image set includes at least two images captured with different parameters; performing image pre-processing on each image of the first image set to obtain a second image set; performing image augmentation on the second image set to obtain a third image set; adding the third image set to a training image data set; and training the artificial intelligence model using the training image data set.

Abstract: A method of fabricating a semiconductor package includes: providing a first die group including a plurality of first dies stacked parallel to a front surface of the first die group; providing a second die group including a plurality of second dies parallel to a front surface of the second die group; providing a base substrate structure comprising a substrate characterized by a lattice crystalline plane extending in a third direction; bonding the first die group on the base substrate structure, wherein the first edge extends in a first direction, and the first direction and the third direction define a first angle; and bonding the second die group on the base substrate structure, wherein the second edge extends in a second direction, and the second direction and the third direction define a second angle, and at least one of the first angle and the second angle is not zero.

Abstract: A method includes forming a dummy component, including: forming through-substrate vias (TSVs) in a substrate; forming a thermal structure over the TSVs, wherein the thermal structure includes metal lines in dielectric layers; forming a bonding layer over the thermal structure; and forming bond pads within the bonding layer; bonding the dummy component to a package component; and bonding a semiconductor die to the package component.

Abstract: Packaged semiconductor devices including high-thermal conductivity molding compounds and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution structure; a first die over and electrically coupled to the first redistribution structure; a first through via over and electrically coupled to the first redistribution structure; an insulation layer extending along the first redistribution structure, the first die, and the first through via; and an encapsulant over the insulation layer, the encapsulant surrounding portions of the first through via and the first die, the encapsulant including conductive fillers at a concentration ranging from 70% to about 95% by volume.