Abstract: A manufacturing method of an electronic package includes the following steps. Multiple chips and a base dielectric layer are provided. A back surface of each chip is fixed to a back surface temporary carrier via a back surface temporary bonding layer. A base dielectric layer surrounds each chip and covers the back surface temporary bonding layer. A material of the base dielectric layer includes a silicate composite material. At least one bridge element is installed on the adjacent chips. An intermediate dielectric layer covering the base dielectric layer, the chips, and the bridge element is formed. Multiple intermediate conductive vias and a redistribution structure are respectively formed on the chips and the intermediate dielectric layer. Multiple conductive bumps are formed on the redistribution structure. The back surface temporary bonding layer and the back surface temporary carrier are removed. An electronic package produced by the manufacturing method is also provided.

Abstract: A method for fabricating an MRAM device is disclosed. The method includes: depositing a first dielectric layer and a second dielectric layer over a semiconductor substrate; depositing a bottom electrode layer over the second dielectric layer, and forming an MTJ stack and a hard mask layer over the bottom electrode layer; patterning the hard mask layer and forming at least one MTJ pillar by etching the MTJ stack with the patterned hard mask layer serving as a mask; depositing a first ILD layer over a top surface of the hard mask layer and on sidewalls of the hard mask layer and MTJ pillar; performing a first etch-back process on the first ILD layer, such that a surface of the first ILD layer on each side of the hard mask layer and the MTJ pillar forms a slope of 40°-70° with respect to a surface of the semiconductor substrate.

Abstract: An artificial intelligent finger-ring device for pre-alarming heart disease, which may detect heart diseases and emit alerts even before heart disease symptoms happen, comprises a detection block, a communication-transmission block, a control block and a power block. The detection block includes a light source emitting green light and a light receiver receiving a response light signal. The green light is incident to a finger of a user and reflected to form the response light signal. The communication-transmission block transmits the response light signal to an external device and receives an analysis result from the external device. The analysis result which is acquired by analyzing the response light signal includes a time-domain index and a frequency-domain index applicable to monitor heart diseases. The control block receives the analysis result and determine whether to emit alerts. The power block supplies electric power to the detection block, the communication-transmission block and the control block.

Abstract: A manufacturing method of an electronic package includes the following steps. Multiple chips are temporarily fixed to a temporary carrier. At least one bridge element is installed on the adjacent chips. A base dielectric layer covering a temporary bonding layer, the chips, and the bridge element is formed. A material of the base dielectric layer includes a silicate composite material. Multiple base conductive vias and a redistribution structure are respectively formed on the chips and the base dielectric layer. Multiple conductive bumps are formed on the redistribution structure. In addition, an electronic package is also provided, which may be produced by the manufacturing method.

Abstract: A miniature pump includes an upper shell, an air bag and a lower shell. The air bag is formed on the upper shell. The lower shell is connected to the upper shell in an air-tight manner. The air bag is compressible to pump air from it and expansible to suck air into it. The lower shell includes two grids for reinforcement so that the lower shell is not deformed when the air bag is compressed on the lower shell.

Abstract: An integrated circuit includes a first nanostructure transistor having a first gate electrode and a second nanostructure transistor having a second gate electrode. A dielectric isolation structure is between the first and second gate electrodes. A gate connection metal is on a portion of the top surface of the first gate electrode and on a portion of a top surface of the second gate electrode. The gate connection metal is patterned to expose other portions of the top surfaces of the first and second gate electrodes adjacent to the dielectric isolation structure. A conductive via contacts the exposed portion of the top surface of the second gate electrode.

Abstract: A semiconductor device a method of forming the same are provided. The method includes forming a fin extending from a substrate and forming a gate dielectric layer along a top surface and sidewalls of the fin. A first thickness of the gate dielectric layer along the top surface of the fin is greater than a second thickness of the gate dielectric layer along the sidewalls of the fin.

Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.

Abstract: A semiconductor package device includes a first semiconductor structure, a second semiconductor structure, and a non-metal dopant. The first semiconductor structure includes a first dielectric bonding layer and a first conductive bonding feature disposed in the first dielectric bonding layer. The second semiconductor structure includes a second dielectric bonding layer bonded to the first dielectric bonding layer and a second conductive bonding feature disposed in the second dielectric bonding layer. The first conductive bonding feature is bonded to the second conductive bonding feature to form an interface therebetween. The non-metal dopant is disposed in at least one of the first conductive bonding feature and the second conductive bonding feature.

Abstract: A semiconductor structure includes a wafer circuit structure, at least one first semiconductor die, at least one first supporting structure, and an encapsulant. The at least one first semiconductor die is disposed over and electrically connected to the wafer circuit structure in a device region of the semiconductor structure. The at least one first supporting structure is disposed over the wafer circuit structure in a peripheral region of the semiconductor structure. The encapsulant is disposed over the wafer circuit structure and encapsulates the at least one first semiconductor die and the at least one first supporting structure, where a thickness of the encapsulant at an edge of the semiconductor structure is less than a thickness of the encapsulant within the device region of the semiconductor structure.

Abstract: A method includes the following steps: providing a first base structure; bonding a plurality of chips to a top surface of the first base structure; bonding two or more dies together using fusion bonding or hybrid bonding to form a die stack; and bonding the die stack to the top surface of the first base structure. A first lateral distance, in a first direction, between a first boundary of the die stack and a boundary of a neighboring chip among the plurality of chips is larger than a first threshold distance.

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

Abstract: A depth information detector includes a light receiving module and a processor. The light receiving module includes a first receiver and a second receiver set at intervals. The first receiver and the second receiver receive a reflected light reflected by an object to be detected at different positions respectively. The processor electrically connects to the light receiving module. The processor is configured for synthesizing the reflected light received by the first receiver and the second receiver into a depth image. The light receiving module also includes a first polarizer and a second polarizer, the first polarizer is on one side of the first receiver, the second polarizer is on one side of the second receiver, a polarization direction of the first polarizer and a polarization direction of the second polarizer are orthogonal to each other. A time-of-flight camera and a depth image acquisition method are further disclosed.

Abstract: An IC device includes an interlayer dielectric (ILD), a first tower structure embedded in the ILD, and a first ring region including a portion of the ILD that extends around the first tower structure. The first tower structure includes a plurality of first conductive patterns in a plurality of metal layers, and a plurality of first vias between the plurality of metal layers along a thickness direction of the IC device. The plurality of first conductive patterns and the plurality of first vias are coupled to each other to form the first tower structure. The plurality of first conductive patterns is confined by the first ring region, without extending beyond the first ring region. The first tower structure is a dummy tower structure.

Abstract: Described is an apparatus of a fifth generation (5G) Evolved Node-B (eNB) operable to communicate with a 5G User Equipment (UE) on a wireless network comprising one or more processors operable to generate one or more 5G Physical Downlink Shared Channel (xPDSCH) transmissions. The one or more processors may be operable to arrange the one or more xPDSCH transmissions for transmission through one or more respectively corresponding beamformed (Tx) beams. The one or more xPDSCH transmissions may carry one or more respectively corresponding 5G System Information Blocks (xSIBs).

Abstract: Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.

Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

Abstract: In some embodiments, the present disclosure relates to a method of forming a metal-insulator-metal (MIM) device. The method may be performed by depositing a bottom electrode layer over a substrate, depositing a dielectric layer over the bottom electrode layer, depositing a top electrode layer over the dielectric layer, and depositing a first titanium getter layer over the top electrode layer. The first titanium getter layer, the top electrode layer, and the dielectric layer are patterned to expose a peripheral portion of the bottom electrode layer. A passivation layer is deposited over the substrate, the first titanium getter layer, and the peripheral portion of the bottom electrode layer.

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.