Patents by Inventor Yuan-Chang Lee
Yuan-Chang Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11967591Abstract: A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.Type: GrantFiled: August 6, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hao Chen, Fong-Yuan Chang, Po-Hsiang Huang, Ching-Yi Lin, Jyh Chwen Frank Lee
-
Patent number: 11929340Abstract: A structure includes a redistribution structure, which includes a bottom layer and a plurality of upper layers over the bottom layer. The redistribution structure also includes a power-ground macro extending from a topmost layer in the plurality of upper layers to a bottommost layer in the plurality of upper layers, and a metal pad in the bottom layer and overlapped by the power-ground macro. The metal pad is electrically disconnected from the power-ground macro.Type: GrantFiled: August 4, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ting-Yu Yeh, Chun-Hua Chang, Fong-Yuan Chang, Jyh Chwen Frank Lee
-
Patent number: 8269112Abstract: A circuit structure and a fabrication method thereof manly use a plurality of wires to connect in series a plurality of pads to form a stretchable circuit. Each of the wires has a first end, a second end and an intermediate segment located between the first end and the second end, wherein the first end and the second end are respectively connected to different pads, and the position of the intermediate segment is higher than the positions of the first end and the second end. Since the connection manner of the wires and the pads has 3-D freedoms, the circuit structure can withstand both horizontal and vertical deformations and has an outstanding reliability.Type: GrantFiled: August 11, 2008Date of Patent: September 18, 2012Assignee: Industrial Technology Research InstituteInventors: Yuan-Chang Lee, Yu-Hua Chen, Ying-Ching Shih, Cheng-Ta Ko
-
Patent number: 8193632Abstract: The three-dimensional conducting structure comprises a substrate, a first redistributed conductor, a second redistributed conductor and an insulator. The substrate has an active surface, a passive surface opposite to the active one, a pad on the active surface and a through hole. The first redistributed conductor comprises a projecting portion and a receiving portion. The projecting portion is projected from the active surface and electrically connected to the pad. The receiving portion is outside the active surface and in contact with the projecting portion, both of which constitute a recess communicating with the through hole. The second redistributed conductor is positioned within the through hole and the recess, in contact with the receiving portion, and extended toward the passive surface along the through hole. The insulator is filled between the second redistributed conductor and the substrate and between the second redistributed conductor and the projecting portion.Type: GrantFiled: July 10, 2009Date of Patent: June 5, 2012Assignee: Industrial Technology Research InstituteInventors: Hsiang-Hung Chang, Shu-Ming Chang, Tzu-Ying Kuo, Yuan-Chang Lee
-
Patent number: 7968799Abstract: A contact structure on a substrate which has at least one contact is provided. The contact structure includes a compliant layer, at least one solder pad, at least one conductive via, and at least one conductive arm. The compliant layer is disposed on the substrate and covers the contact. The solder pad is disposed on the surface of the compliant layer which is at the opposite side of the substrate. The conductive via is disposed in the compliant layer and is connected to the contact. The conductive arm is disposed on the surface of the compliant layer in opposite to the substrate, and two ends of the conductive arm are respectively connected to the conductive via and the solder pad. Furthermore, a method for fabricating the contact structure, an interposer and an electrical package using the contact structure are provided.Type: GrantFiled: July 5, 2007Date of Patent: June 28, 2011Assignee: Industrial Technology Research InstituteInventor: Yuan-Chang Lee
-
Publication number: 20100032830Abstract: The three-dimensional conducting structure comprises a substrate, a first redistributed conductor, a second redistributed conductor and an insulator. The substrate has an active surface, a passive surface opposite to the active one, a pad on the active surface and a through hole. The first redistributed conductor comprises a projecting portion and a receiving portion. The projecting portion is projected from the active surface and electrically connected to the pad. The receiving portion is outside the active surface and in contact with the projecting portion, both of which constitute a recess communicating with the through hole. The second redistributed conductor is positioned within the through hole and the recess, in contact with the receiving portion, and extended toward the passive surface along the through hole. The insulator is filled between the second redistributed conductor and the substrate and between the second redistributed conductor and the projecting portion.Type: ApplicationFiled: July 10, 2009Publication date: February 11, 2010Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hsiang-Hung Chang, Shu-Ming Chang, Tzu-Ying Kuo, Yuan-Chang Lee
-
Publication number: 20090173529Abstract: A circuit structure and a fabrication method thereof manly use a plurality of wires to connect in series a plurality of pads to form a stretchable circuit. Each of the wires has a first end, a second end and an intermediate segment located between the first end and the second end, wherein the first end and the second end are respectively connected to different pads, and the position of the intermediate segment is higher than the positions of the first end and the second end. Since the connection manner of the wires and the pads has 3-D freedoms, the circuit structure can withstand both horizontal and vertical deformations and has an outstanding reliability.Type: ApplicationFiled: August 11, 2008Publication date: July 9, 2009Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yuan-Chang Lee, Yu-Hua Chen, Ying-Ching Shih, Cheng-Ta Ko
-
Publication number: 20080265410Abstract: A wafer level package includes a substrate, a passivation layer, an elastic layer, a first insulation layer, a metal trace, a second insulation layer, and a bump. The passivation layer is formed on the substrate, and has one pad. The elastic layer is formed on the passivation layer. The first insulation layer is formed on the passivation layer and the elastic layer, and has a junction in contact with the pad. The metal trace is formed on the first insulation layer. The second insulation layer is formed on the metal trace, and a groove is formed correspondingly above the elastic layer. The bump is formed in the groove. An annular trench can be further formed around the bump. A groove can be furthermore formed in the first insulation layer correspondingly below the bump.Type: ApplicationFiled: October 30, 2007Publication date: October 30, 2008Inventors: Shu-Ming Chang, Yu-Jiau Hwang, Yuan-Chang Lee
-
Publication number: 20080093115Abstract: A contact structure on a substrate which has at least one contact is provided. The contact structure includes a compliant layer, at least one solder pad, at least one conductive via, and at least one conductive arm. The compliant layer is disposed on the substrate and covers the contact. The solder pad is disposed on the surface of the compliant layer which is at the opposite side of the substrate. The conductive via is disposed in the compliant layer and is connected to the contact. The conductive arm is disposed on the surface of the compliant layer in opposite to the substrate, and two ends of the conductive arm are respectively connected to the conductive via and the solder pad. Furthermore, a method for fabricating the contact structure, an interposer and an electrical package using the contact structure are provided.Type: ApplicationFiled: July 5, 2007Publication date: April 24, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventor: Yuan-Chang Lee
-
Patent number: D1016698Type: GrantFiled: October 27, 2021Date of Patent: March 5, 2024Assignee: Foxtron Vehicle Technologies Co., Ltd.Inventors: Tse-Min Cheng, Ming-Chang Lin, Yuan-Jie He, Chiao-Chi Lin, Lu-Han Lee