Abstract: Provided are a system and a method for optimization of network function management and computer readable medium thereof that develop an OAM system architecture compatible with a standard MANO framework set by ETSI, so as to effectively integrate and manage the resources and situation configurations of the network elements (including VNF and CNF) of different manufacturers. Therefore, containment management for various network elements may be flexibly integrated, advantages of the standard MANO framework may be preserved, cost for customized development of various OAM systems and the information transmission therefrom may be reduced, and overall efficiency is increased.

Abstract: A method for manufacturing an optical sensor is provided. The operations of the method for manufacturing the optical sensor includes providing a semiconductive layer having an electrical circuit area and an optical sensing area; forming a first electrical contact directly over the electrical circuit area; forming a first light guiding part directly over the optical sensing area simultaneously with forming the first electrical contact; forming a first metal layer directly over the first electrical contact; forming a second light guiding part directly over the first light guiding part simultaneously with forming a second electrical contact directly over the first electrical contact; forming a thick metal layer over the electrical circuit area and an optical sensing area; and forming an aperture in the thick metal layer, wherein the aperture aligning with the optical sensing area.

Abstract: A method for manufacturing an optical sensor is provided. The operations of the method for manufacturing the optical sensor includes providing a semiconductive layer having an electrical circuit area and an optical sensing area; forming a first electrical contact directly over the electrical circuit area; forming a first light guiding part directly over the optical sensing area simultaneously with forming the first electrical contact; forming a first metal layer directly over the first electrical contact; forming a second light guiding part directly over the first light guiding part simultaneously with forming a second electrical contact directly over the first electrical contact; forming a thick metal layer over the electrical circuit area and an optical sensing area; and forming an aperture in the thick metal layer, wherein the aperture aligning with the optical sensing area.

Abstract: An optical sensor includes a semiconductive layer having an electrical circuit area and an optical sensing area, a sample-holding portion over the optical sensing area, a light-guiding structure between the sample-holding portion and the optical sensing area, and an electrical interconnect structure over the electrical circuit area. The electrical interconnect structure is integrally formed with the light-guiding structure, and the light-guiding structure is configured to direct an emitting light from the sample-holding portion to the optical sensing area.

Abstract: A method of generating a gain of an image frame according to a look up table of gain which is set up based on luminance sensitivity of human eyes is proposed. The method includes setting a gain of an image frame to 1, scanning images of a plurality of front rows of the image frame, averaging the images of the plurality of the front rows of the image frame to generate an average value of the images of the plurality of the front rows of the image frame, finding a gain from the look up table of gain according to the average value of the images of the plurality of the front rows of the image frame, and adjusting remaining rows of the image frame according to the gain to generate images of the remaining rows of the image frame.

Abstract: Circuitry for reducing fixed pattern noise in an image processing system with a 4-T (4 transistors) pixel and a method thereof is proposed. The image processing system includes two voltage sources, two current sources, a 4-T pixel, a second portion of a linearized source follower, a ping pong memory, a PGA, and auto-zero circuitry. By coupling the auto-zero circuitry to the PGA, an open loop is formed to clamp the output of an op amp of the PGA to a stable reference when resetting the PGA so as to remove DC offsets at the output terminal of the op amp.

Abstract: A voltage generating apparatus is disclosed. The voltage generating apparatus includes a first N-type transistor and an enhancement MOSFET transistor. The first N-type transistor has a first drain/source coupled to a first voltage, a second drain/source generating a first output voltage, and a gate coupled to a second voltage. The enhancement MOSFET transistor has a first drain/source coupled to the second drain/source of the first N-type transistor, and a second drain/source and a gate coupled to a second voltage. The first N-type transistor is a depletion metal oxide semiconductor field effect transistor (MOSFET).

Abstract: A voltage generating apparatus is disclosed. The voltage generating apparatus includes a first N-type transistor and an enhancement MOSFET transistor. The first N-type transistor has a first drain/source coupled to a first voltage, a second drain/source generating a first output voltage, and a gate coupled to a second voltage. The enhancement MOSFET transistor has a first drain/source coupled to the second drain/source of the first N-type transistor, and a second drain/source and a gate coupled to a second voltage. The first N-type transistor is a depletion metal oxide semiconductor field effect transistor (MOSFET).

Abstract: A method of generating a gain of an image frame according to a look up table of gain which is set up based on luminance sensitivity of human eyes is proposed. The method includes setting a gain of an image frame to 1, scanning images of a plurality of front rows of the image frame, averaging the images of the plurality of the front rows of the image frame to generate an average value of the images of the plurality of the front rows of the image frame, finding a gain from the look up table of gain according to the average value of the images of the plurality of the front rows of the image frame, and adjusting remaining rows of the image frame according to the gain to generate images of the remaining rows of the image frame.

Abstract: Circuitry for reducing fixed pattern noise in an image processing system with a 4-T (4 transistors) pixel and a method thereof is proposed. The image processing system includes two voltage sources, two current sources, a 4-T pixel, a second portion of a linearized source follower, a ping pong memory, a PGA, and auto-zero circuitry. By coupling the auto-zero circuitry to the PGA, an open loop is formed to clamp the output of an op amp of the PGA to a stable reference when resetting the PGA so as to remove DC offsets at the output terminal of the op amp.

Abstract: A defect detection system and related method take advantage of multilevel detection technique for detecting defects on an integrated circuit. The defect detection system utilizes an analog-to-digital converter for converting an analog sensing signal into an output code having a plurality of bits. The defect detection methods include an open test method and a short test method. The open and short test methods both include a calibrating method and a testing method individually. The calibrating method functions to determine a preset reference voltage for the analog-to-digital converter based on a predetermined code. The testing method makes use of the preset reference voltage and the predetermined code for generating the output code having a plurality of bits. The output code is then utilized to determine whether or not there are open or short defects on the integrated circuit and to classify the defects.

Abstract: A defect detection system and related method take advantage of multilevel detection technique for detecting defects on an integrated circuit. The defect detection system utilizes an analog-to-digital converter for converting an analog sensing signal into an output code having a plurality of bits. The defect detection methods include an open test method and a short test method. The open and short test methods both include a calibrating method and a testing method individually. The calibrating method functions to determine a preset reference voltage for the analog-to-digital converter based on a predetermined code. The testing method makes use of the preset reference voltage and the predetermined code for generating the output code having a plurality of bits. The output code is then utilized to determine whether or not there are open or short defects on the integrated circuit and to classify the defects.