Patents by Inventor Yuan-Chen Hsu
Yuan-Chen Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12288716Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.Type: GrantFiled: April 29, 2024Date of Patent: April 29, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hsien Huang, I-Li Chen, Pin-Wen Chen, Yuan-Chen Hsu, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
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Patent number: 12252783Abstract: Low-flow tungsten chemical vapor deposition (CVD) techniques described herein provide substantially uniform deposition of tungsten on a semiconductor substrate. In some implementations, a flow of a processing vapor is provided to a CVD processing chamber such that a flow rate of tungsten hexafluoride in the processing vapor results in the tungsten layer being grown at a slower rate than a higher flow rate of the tungsten hexafluoride to promote substantially uniform growth of the tungsten layer. In this way, the low-flow tungsten CVD techniques may be used to achieve similar surface uniformity performance to an atomic layer deposition (ALD) while being a faster deposition process relative to ALD (e.g., due to the lower deposition rate and large quantity of alternating processing cycles of ALD). This reduces the likelihood of defect formation in the tungsten layer while increasing the throughput of semiconductor device processing for the semiconductor substrate (and other semiconductor substrates).Type: GrantFiled: August 6, 2021Date of Patent: March 18, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pin-Wen Chen, Yuan-Chen Hsu, Ken-Yu Chang
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Publication number: 20240282626Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas.Type: ApplicationFiled: April 29, 2024Publication date: August 22, 2024Inventors: Chun-Hsien Huang, I-Li Chen, Pin-Wen Chen, Yuan-Chen Hsu, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
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Patent number: 12002712Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.Type: GrantFiled: June 30, 2022Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Hsien Huang, I-Li Chen, Pin-Wen Chen, Yuan-Chen Hsu, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
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Publication number: 20230038744Abstract: Low-flow tungsten chemical vapor deposition (CVD) techniques described herein provide substantially uniform deposition of tungsten on a semiconductor substrate. In some implementations, a flow of a processing vapor is provided to a CVD processing chamber such that a flow rate of tungsten hexafluoride in the processing vapor results in the tungsten layer being grown at a slower rate than a higher flow rate of the tungsten hexafluoride to promote substantially uniform growth of the tungsten layer. In this way, the low-flow tungsten CVD techniques may be used to achieve similar surface uniformity performance to an atomic layer deposition (ALD) while being a faster deposition process relative to ALD (e.g., due to the lower deposition rate and large quantity of alternating processing cycles of ALD). This reduces the likelihood of defect formation in the tungsten layer while increasing the throughput of semiconductor device processing for the semiconductor substrate (and other semiconductor substrates).Type: ApplicationFiled: August 6, 2021Publication date: February 9, 2023Inventors: Pin-Wen CHEN, Yuan-Chen HSU, Ken-Yu CHANG
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Publication number: 20220352020Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas.Type: ApplicationFiled: June 30, 2022Publication date: November 3, 2022Inventors: Chun-Hsien Huang, I-Li Chen, Pin-Wen Chen, Yuan-Chen Hsu, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
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Patent number: 11410880Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.Type: GrantFiled: April 23, 2019Date of Patent: August 9, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hsien Huang, I-Li Chen, Pin-Wen Chen, Yuan-Chen Hsu, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
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Publication number: 20200343135Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.Type: ApplicationFiled: April 23, 2019Publication date: October 29, 2020Inventors: Chun-Hsien Huang, I-Li Chen, Pin-Wen Chen, Yuan-Chen Hsu, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
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Patent number: 10177494Abstract: A pluggable transceiver module is provided. The pluggable transceiver module is adapted to be inserted to a cage. The pluggable transceiver module includes a housing, a cover, a latch, an elastic element, and a bail bar. The latch is sandwiched between the cover and the housing. The latch includes a fastening portion. The elastic element is disposed on the housing and abuts the latch. The bail bar abuts the latch. The bail bar is rotated between a first bar position and a second bar position. When the bail bar is in the first bar position, the fastening portion is affixed to the cage. When the bail bar is rotated from the first bar position to the second bar position, the latch is moved in an oblique direction, and the fastening portion is separated from the cage.Type: GrantFiled: November 29, 2017Date of Patent: January 8, 2019Assignee: DELTA ELECTRONICS, INC.Inventors: Chen-Mao Lu, Chieh-Tse Huang, Yuan-Chen Hsu
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Publication number: 20180375254Abstract: A pluggable transceiver module is provided. The pluggable transceiver module is adapted to be inserted to a cage. The pluggable transceiver module includes a housing, a cover, a latch, an elastic element, and a bail bar. The latch is sandwiched between the cover and the housing. The latch includes a fastening portion. The elastic element is disposed on the housing and abuts the latch. The bail bar abuts the latch. The bail bar is rotated between a first bar position and a second bar position. When the bail bar is in the first bar position, the fastening portion is affixed to the cage. When the bail bar is rotated from the first bar position to the second bar position, the latch is moved in an oblique direction, and the fastening portion is separated from the cage.Type: ApplicationFiled: November 29, 2017Publication date: December 27, 2018Inventors: Chen-Mao LU, Chieh-Tse HUANG, Yuan-Chen HSU
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Publication number: 20140041909Abstract: A method for reducing roughens of the metals on a ceramic substrate having metal filled via holes, comprising forming via holes, a seed layer, and through film coating, exposure and development process followed by multiple steps of DC electroplating to achieve copper circuit with desired surface roughness.Type: ApplicationFiled: July 17, 2013Publication date: February 13, 2014Inventors: Hsiang-Wei TSENG, Kuan-Chou Chen, Han-Chung Chang, Cheng-Feng Chou, Chan-Li Lin, Yuan-Chen Hsu