Patents by Inventor Yuan-Chen Tsai

Yuan-Chen Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7435642
    Abstract: A method of evaluating the uniformity of the thickness of the polysilicon gate layer is provided. A substrate having a dense trenches area and a sparse trenches area is provided. A plurality of first trench isolation structures are formed in the sparse trenches area of the substrate and a plurality of second trench isolation structures are simultaneously formed in the dense trenches area of the substrate. A mask layer is formed between the gaps of the first and the second trench isolation structures. A portion of the first trench isolation structures of the sparse trenches area is then removed. Then, the mask layer is removed until the surface of the substrate is exposed. A polysilicon gate layer is formed over the substrate. Finally, a planarization process is performed to remove a portion of the polysilicon gate layer.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: October 14, 2008
    Assignees: Powerchip Semiconductor Corp., Renesas Technology Corp.
    Inventors: Ta-Jen Wang, Yuan-Chen Tsai, Shih-Jan Tung, Matsuo Hiroshi
  • Publication number: 20080113485
    Abstract: A method of evaluating the uniformity of the thickness of the polysilicon gate layer is provided. A substrate having a dense trenches area and a sparse trenches area is provided. A plurality of first trench isolation structures are formed in the sparse trenches area of the substrate and a plurality of second trench isolation structures are simultaneously formed in the dense trenches area of the substrate. A mask layer is formed between the gaps of the first and the second trench isolation structures. A portion of the first trench isolation structures of the sparse trenches area is then removed. Then, the mask layer is removed until the surface of the substrate is exposed. A polysilicon gate layer is formed over the substrate. Finally, a planarization process is performed to remove a portion of the polysilicon gate layer.
    Type: Application
    Filed: November 14, 2006
    Publication date: May 15, 2008
    Applicant: POWERCHIP SEMICONDUCTOR CORP.
    Inventors: Ta-Jen Wang, Yuan-Chen Tsai, Shih-Jan Tung
  • Patent number: 6174793
    Abstract: A method for enhancing adhesion ability between copper and silicon nitride is disclosed. The present method comprises following steps: first, provide a substrate and then form a copper layer on the substrate; second, form a copper phosphide layer on the copper layer; and finally, form a silicon nitride layer on the copper phosphide layer. Herein, the copper phosphide layer is formed by a plasma enhanced chemical vapor deposition process. Therefore, any copper oxide layer that covers copper layer is replaced by the silicon phosphide layer and then adhesion between copper and silicon nitride is improved. Moreover, the silicon phosphide comprises two advantages: low resistance than copper oxide and efficiently prevent copper diffuses into surrounding dielectric layer.
    Type: Grant
    Filed: October 11, 1999
    Date of Patent: January 16, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Yuan-Chen Tsai, Chih-Chien Liu, Juan-Yuan Wu