Abstract: The invention provides a photoresist coating method, which comprises the following steps: providing a wafer with a pattern on the wafer, placing the wafer on a spinner, injecting a photoresist on a central region of the wafer from a nozzle, and carrying out a spin coating step, the spin coating step comprises: turning on the spinner to rotate the spinner to a first rotation speed, and raising the first rotation speed to a second rotation speed, and performing a plurality of brakes during the process of maintaining the second rotation speed, so that the second rotation speed instantly drops to a third rotation speed, and then rises to the second rotation speed again.

Abstract: The invention provides a semiconductor manufacturing process, which comprises the following steps: using a computer system to define plurality of shots on a wafer range, distributing a plurality of observation points in each shot, finding out parts of incomplete shots from all of the shots, calculating the number of observation points in each incomplete shot, eliminating the incomplete shots with the number less than 3 observation points, counting all observation points in the remaining incomplete shots, and deleting a part of observation points until the total number of observation points meets a preset total number, and uniformly distributing all observation points, and performing an overlay measurement step on the remaining observation points to generate an offset vector map.

Abstract: A method for aligning to a pattern on a wafer is disclosed. The method includes the steps of obtaining a first inline image from a first sample wafer, obtaining a first contour pattern of an alignment mark pattern from the first inline image, using the first contour pattern to generate a first synthetic image in black and white pixels of only two grayscale levels, using the first synthetic image as a reference to recognize the alignment mark pattern on a tested wafer, and aligning to a tested pattern on the tested wafer according to a position of the alignment mark pattern on the tested wafer and a coordinate information.

Abstract: A method for aligning to a pattern on a wafer is disclosed. The method includes the steps of obtaining a first inline image from a first sample wafer, obtaining a first contour pattern of an alignment mark pattern from the first inline image, using the first contour pattern to generate a first synthetic image in black and white pixels, using the first synthetic image as a reference to recognize the alignment mark pattern on a tested wafer, and aligning to a tested pattern on the tested wafer according to a position of the alignment mark pattern on the tested wafer and a coordinate information.

Abstract: The invention provides a correction and compensation method in a semiconductor manufacturing process. The method includes the following steps: providing a machine, the machine is at least used for exposure manufacturing of a first product and a second product, performing period maintenance (PM) on the machine, recording an original offset map before and after the period maintenance of the machine is performed, the original offset map has an original exposure size, and adjusting the original exposure size of the original offset map to correspond to a first exposure size of the first product, and performing a first offset compensation correction on the first product. And adjusting the original exposure size of the original offset map to correspond to a second exposure size of the second product, and performing a second offset compensation correction on the second product.

Abstract: A reticle thermal expansion calibration method includes exposing a group of wafers and generating a sub-recipe, performing data mining and data parsing to generate a plurality of overlay parameters, extracting a plurality of predetermined parameters from the plurality of overlay parameters, performing a linear regression on each of the predetermined parameters, and generating a coefficient of determination for each of the predetermined parameters.

Abstract: A manufacturing method of a contact structure includes the following steps. A substrate is provided, and the substrate includes a first region and a second region. A dielectric layer is formed on the substrate. A photoresist layer is formed on the dielectric layer. An exposure process is performed. The exposure process includes first exposure steps and second exposure steps. Each of the first exposure steps is performed to a part of the first region of the substrate. Each of the second exposure steps is performed to a part of the second region of the substrate. Each of the second exposure steps is performed with a first overlay shift by a first predetermined distance. A develop process is performed for forming openings in the photoresist layer.

Abstract: A method for aligning to a pattern on a wafer is disclosed. The method includes the steps of obtaining a first inline image from a first sample wafer, obtaining a first contour pattern of an alignment mark pattern from the first inline image, using the first contour pattern to generate a first synthetic image in black and white pixels, using the first synthetic image as a reference to recognize the alignment mark pattern on a tested wafer, and aligning to a tested pattern on the tested wafer according to a position of the alignment mark pattern on the tested wafer and a coordinate information.

Abstract: A manufacturing method of a contact structure includes the following steps. A substrate is provided, and the substrate includes a first region and a second region. A dielectric layer is formed on the substrate. A photoresist layer is formed on the dielectric layer. An exposure process is performed. The exposure process includes first exposure steps and second exposure steps. Each of the first exposure steps is performed to a part of the first region of the substrate. Each of the second exposure steps is performed to a part of the second region of the substrate. Each of the second exposure steps is performed with a first overlay shift by a first predetermined distance. A develop process is performed for forming openings in the photoresist layer.

Abstract: An asymmetry compensation method used in a lithography overlay process and including steps of: providing a first substrate, wherein a circuit layout is disposed on the first substrate, a first mask layer and a second mask layer together having an x-axis allowable deviation range and an y-axis allowable deviation range relative to the circuit layout are stacked sequentially on the circuit layout, wherein the x-axis allowable deviation range is unequal to the y-axis allowable deviation range; and calculating an x-axis final compensation parameter and an y-axis final compensation parameter base on the unequal x-axis allowable deviation range and the y-axis allowable deviation range.

Abstract: The present invention provides a photo-mask for manufacturing structures on a semiconductor substrate, which comprises a photo-mask substrate, a first pattern, a second pattern and a forbidden pattern. A first active region, a second active region are defined on the photo-mask substrate, and a region other than the first active region and the second active region are defined as a forbidden region. The first pattern is disposed in the first active region and corresponds to a first structure on the semiconductor substrate. The second pattern is disposed in the second active region and corresponds to a second structure on the semiconductor substrate. The forbidden pattern is disposed in the forbidden region, wherein the forbidden pattern has a dimension beyond resolution capability of photolithography and is not used to form any corresponding structure on the semiconductor substrate. The present invention further provides a method of manufacturing semiconductor structures.

Abstract: A method of correcting an overlay error includes the following steps. First, an overlay mark disposed on a substrate is captured so as to generate overlay mark information. The overlay mark includes at least a pair of first mark patterns and at least a second mark pattern above the first mark patterns. Then, the overlay mark information is calculated to generate an offset value between two first mark patterns and to generate a shift value between the second mark pattern and one of the first mark patterns. Finally, the offset value is used to compensate the shift value so as to generate an amended shift value.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes the following steps. A substrate including a first transistor having a first conductivity type, a second transistor having a second conductivity type and a third transistor having the first conductivity type is formed. An inner-layer dielectric layer is formed on the substrate, and includes a first gate trench corresponding to the first transistor, a second gate trench corresponding to the second transistor and a third gate trench corresponding to the third transistor. A work function metal layer is formed on the inner-layer dielectric layer. An anti-reflective layer is coated on the work function metal layer. The anti-reflective layer on the second transistor and on the top portion of the third gate trench is removed to expose the work function metal layer. The exposed work function metal layer is removed.

Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first gate and a second gate respectively formed in a first region and a second region is provided. An underlayer is formed on the substrate to cover the first gate in the first region and the second gate in the second region. A patterned mask with a predetermined thickness is formed on the underlayer in the first region. The underlayer corresponding to the second gate in the second region is removed by the patterned mask to expose the second gate, wherein the underlayer corresponding to the first gate in the first region is partially consumed to expose part of the first gate.

Abstract: The present invention provides a photo-mask for manufacturing structures on a semiconductor substrate, which comprises a photo-mask substrate, a first pattern, a second pattern and a forbidden pattern. A first active region, a second active region are defined on the photo-mask substrate, and a region other than the first active region and the second active region are defined as a forbidden region. The first pattern is disposed in the first active region and corresponds to a first structure on the semiconductor substrate. The second pattern is disposed in the second active region and corresponds to a second structure on the semiconductor substrate. The forbidden pattern is disposed in the forbidden region, wherein the forbidden pattern has a dimension beyond resolution capability of photolithography and is not used to form any corresponding structure on the semiconductor substrate. The present invention further provides a method of manufacturing semiconductor structures.

Abstract: An asymmetry compensation method used in a lithography overlay process and including steps of: providing a first substrate, wherein a circuit layout is disposed on the first substrate, a first mask layer and a second mask layer together having an x-axis allowable deviation range and an y-axis allowable deviation range relative to the circuit layout are stacked sequentially on the circuit layout, wherein the x-axis allowable deviation range is unequal to the y-axis allowable deviation range; and calculating an x-axis final compensation parameter and an y-axis final compensation parameter base on the unequal x-axis allowable deviation range and the y-axis allowable deviation range.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes the following steps. A substrate including a first transistor having a first conductivity type, a second transistor having a second conductivity type and a third transistor having the first conductivity type is formed. An inner-layer dielectric layer is formed on the substrate, and includes a first gate trench corresponding to the first transistor, a second gate trench corresponding to the second transistor and a third gate trench corresponding to the third transistor. A work function metal layer is formed on the inner-layer dielectric layer. An anti-reflective layer is coated on the work function metal layer. The anti-reflective layer on the second transistor and on the top portion of the third gate trench is removed to expose the work function metal layer. The exposed work function metal layer is removed.

Abstract: A method of correcting an overlay error includes the following steps. First, an overlay mark disposed on a substrate is captured so as to generate overlay mark information. The overlay mark includes at least a pair of first mark patterns and at least a second mark pattern above the first mark patterns. Then, the overlay mark information is calculated to generate an offset value between two first mark patterns and to generate a shift value between the second mark pattern and one of the first mark patterns. Finally, the offset value is used to compensate the shift value so as to generate an amended shift value.

Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first gate and a second gate respectively formed in a first region and a second region is provided. An underlayer is formed on the substrate to cover the first gate in the first region and the second gate in the second region. A patterned mask with a predetermined thickness is formed on the underlayer in the first region. The underlayer corresponding to the second gate in the second region is removed by the patterned mask to expose the second gate, wherein the underlayer corresponding to the first gate in the first region is partially consumed to expose part of the first gate.

Abstract: A photoresist removal method is described. A substrate having thereon a positive photoresist layer to be removed is provided. The positive photoresist layer is UV-exposed without using a photomask. A development liquid is used to remove the UV-exposed positive photoresist layer. The substrate as provided may further have thereon a sacrificial masking layer under the positive photoresist layer. The sacrificial masking layer is removed after the UV-exposed positive photoresist layer is removed.