Abstract: A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.

Abstract: A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.

Abstract: A memory device includes a substrate. A first dielectric layer is disposed over the substrate. A plurality of conductive layers and a plurality of dielectric layers are alternately and horizontally disposed on the substrate. A channel column structure is disposed on the substrate and in the conductive layers and the dielectric layers. A side wall of the channel column structure is in contact with the plurality of conductive layers. A second dielectric layer covers the first dielectric layer. A conductive column structure is in the first and second dielectric layers, adjacent to the channel column structure, and in contact with one of the plurality of conductive layers. The conductive column structure includes a liner insulating layer as a shell layer.

Abstract: A memory device includes a substrate. A first dielectric layer is disposed over the substrate. A plurality of conductive layers and a plurality of dielectric layers are alternately and horizontally disposed on the substrate. A channel column structure is disposed on the substrate and in the conductive layers and the dielectric layers. A side wall of the channel column structure is in contact with the plurality of conductive layers. A second dielectric layer covers the first dielectric layer. A conductive column structure is in the first and second dielectric layers, adjacent to the channel column structure, and in contact with one of the plurality of conductive layers. The conductive column structure includes a liner insulating layer as a shell layer.

Abstract: A semiconductor structure for three-dimensional memory device and a manufacturing method thereof are provided. In the manufacturing method, clean plasma is used to clean the impurity doped regions, formed by slit etching, in the surface layer of the substrate to decrease the contact resistance between substrate and conductive plugs formed in the slits. The bottom part of the conductive plugs each has a reduced neck structure and an enlarged bottom structure.

Abstract: A semiconductor structure for three-dimensional memory device and a manufacturing method thereof are provided. In the manufacturing method, clean plasma is used to clean the impurity doped regions, formed by slit etching, in the surface layer of the substrate to decrease the contact resistance between substrate and conductive plugs formed in the slits. The bottom part of the conductive plugs each has a reduced neck structure and an enlarged bottom structure.

Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.

Abstract: A three-dimensional non-volatile memory and a method of manufacturing the same are provided. The three-dimensional non-volatile memory includes a substrate, a charge storage structure, a stacked structure and a channel layer. The charge storage structure is disposed on the substrate. The stacked structure is disposed at a side of the charge storage structure and includes insulating layers, gates, a buffer layer and a barrier layer. The insulating layers and the gates are alternately stacked. The buffer layer is disposed between each of the gates and the charge storage structure and on the surfaces of the insulating layers. The barrier layer is disposed between each of the gates and the buffer layer. An end of the gate is convex with respect to an end of the barrier layer in a direction away from the channel layer.

Abstract: A three-dimensional non-volatile memory and a method of manufacturing the same are provided. The three-dimensional non-volatile memory includes a substrate, a charge storage structure, a stacked structure and a channel layer. The charge storage structure is disposed on the substrate. The stacked structure is disposed at a side of the charge storage structure and includes insulating layers, gates, a buffer layer and a barrier layer. The insulating layers and the gates are alternately stacked. The buffer layer is disposed between each of the gates and the charge storage structure and on the surfaces of the insulating layers. The barrier layer is disposed between each of the gates and the buffer layer. An end of the gate is convex with respect to an end of the barrier layer in a direction away from the channel layer.

Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.

Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.

Abstract: Provided is a memory device including a plurality of first conductive line layers, a plurality of support structures, and a charge storage layer. Each of the first conductive line layers extends along a plane defined by a first direction and a second direction. Each of the first conductive line layers includes a plurality of first conductive lines extending along the first direction. The support structures are located between the adjacent first conductive line layers. The charge storage layer covers upper surfaces, lower surfaces, and two side surfaces of the first conductive lines and surfaces of the support structures.

Abstract: Provided is a memory device including a plurality of first conductive line layers, a plurality of support structures, and a charge storage layer. Each of the first conductive line layers extends along a plane defined by a first direction and a second direction. Each of the first conductive line layers includes a plurality of first conductive lines extending along the first direction. The support structures are located between the adjacent first conductive line layers. The charge storage layer covers upper surfaces, lower surfaces, and two side surfaces of the first conductive lines and surfaces of the support structures.

Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.

Abstract: A semiconductor device has a first layer formed on a substrate. A mask layer is formed and patterned above the first layer. The first layer is etched partially through. A second layer is formed over the first layer. The first and second layers are etched by a non-lithography process.

Abstract: The present invention discloses a phosphorescent tris-chelated transition metal complex comprising i) two identical non-conjugated cyclometalated ligands being incorporated into a coordination sphere thereof with a transition metal, and one ligated chromophore being incorporated into the coordination sphere; or ii) one non-conjugated cyclometalated ligand forming a coordination sphere thereof with a transition metal, and two ligated chromophores being incorporated into the coordination sphere, wherein the metal is iridium, platinum, osmium or ruthenium, and the ligated chromophore possesses a relatively lower energy gap in comparison with that of the non-conjugated cyclometalated ligand, the latter afforded an effective barrier for inhibiting the ligand-to-ligand charge transfer process, so that a subsequent radiative decay from an excited state of these transition complexes will be confined to the single ligated chromophore.

Abstract: The present invention discloses a phosphorescent tris-chelated transition metal complex comprising i) two identical non-conjugated cyclometalated ligands being incorporated into a coordination sphere thereof with a transition metal, and one ligated chromophore being incorporated into the coordination sphere; or ii) one non-conjugated cyclometalated ligand forming a coordination sphere thereof with a transition metal, and two ligated chromophores being incorporated into the coordination sphere, wherein the metal is iridium, platinum, osmium or ruthenium, and the ligated chromophore possesses a relatively lower energy gap in comparison with that of the non-conjugated cyclometalated ligand, the latter afforded an effective barrier for inhibiting the ligand-to-ligand charge transfer process, so that a subsequent radiative decay from an excited state of these transition complexes will be confined to the single ligated chromophore.

Abstract: The present invention discloses a phosphorescent tris-chelated transition metal complex comprising i) two identical non-conjugated cyclometalated ligands being incorporated into a coordination sphere thereof with a transition metal, and one ligated chromophore being incorporated into the coordination sphere; or ii) one non-conjugated cyclometalated ligand forming a coordination sphere thereof with a transition metal, and two ligated chromophores being incorporated into the coordination sphere, wherein the metal is iridium, platinum, osmium or ruthenium, and the ligated chromophore possesses a relatively lower energy gap in comparison with that of the non-conjugated cyclometalated ligand, the latter afforded an effective barrier for inhibiting the ligand-to-ligand charge transfer process, so that a subsequent radiative decay from an excited state of these transition complexes will be confined to the single ligated chromophore.

Abstract: The present invention discloses a phosphorescent tris-chelated transition metal complex comprising i) two identical non-conjugated cyclometalated ligands being incorporated into a coordination sphere thereof with a transition metal, and one ligated chromophore being incorporated into the coordination sphere; or ii) one non-conjugated cyclometalated ligand forming a coordination sphere thereof with a transition metal, and two ligated chromophores being incorporated into the coordination sphere, wherein the metal is iridium, platinum, osmium or ruthenium, and the ligated chromophore possesses a relatively lower energy gap in comparison with that of the non-conjugated cyclometalated ligand, the latter afforded an effective barrier for inhibiting the ligand-to-ligand charge transfer process, so that a subsequent radiative decay from an excited state of these transition complexes will be confined to the single ligated chromophore.

Abstract: The present invention discloses a phosphorescent tris-chelated transition metal complex comprising i) two identical non-conjugated cyclometalated ligands being incorporated into a coordination sphere thereof with a transition metal, and one ligated chromophore being incorporated into the coordination sphere; or ii) one non-conjugated cyclometalated ligand forming a coordination sphere thereof with a transition metal, and two ligated chromophores being incorporated into the coordination sphere, wherein the metal is iridium, platinum, osmium or ruthenium, and the ligated chromophore possesses a relatively lower energy gap in comparison with that of the non-conjugated cyclometalated ligand, the latter afforded an effective barrier for inhibiting the ligand-to-ligand charge transfer process, so that a subsequent radiative decay from an excited state of these transition complexes will be confined to the single ligated chromophore.