Abstract: A system for managing software-defined persistent memory includes a CPU, a PCIe switch, one or more random access memory modules, and one or more NVMe SSDs. The PCIe switch is configured to communicate with one or more host devices. The CPU and the PCIe switch are configured to generate, for each host device, a persistent memory controller data structure that has configuration data to enable the CPU and the PCIe switch to emulate a persistent memory controller when interacting with the host device. The CPU and the PCIe switch are configured to receive instructions from the one or more host devices and persistently store write data in one or more NVMe SSDs or retrieve read data from the one or more NVMe SSDs based on the instructions from the one or more host devices, and use at least a portion of the RAM as cache memory to temporarily store at least one of the read data from the one or more NVMe SSDs or the write data intended to be persistently stored in the one or more NVMe SSDs.

Abstract: A system for managing software-defined persistent memory includes a CPU, a PCIe switch, one or more random access memory modules, and one or more NVMe SSDs. The PCIe switch is configured to communicate with one or more host devices. The CPU and the PCIe switch are configured to generate, for each host device, a persistent memory controller data structure that has configuration data to enable the CPU and the PCIe switch to emulate a persistent memory controller when interacting with the host device. The CPU and the PCIe switch are configured to receive instructions from the one or more host devices and persistently store write data in one or more NVMe SSDs or retrieve read data from the one or more NVMe SSDs based on the instructions from the one or more host devices, and use at least a portion of the RAM as cache memory to temporarily store at least one of the read data from the one or more NVMe SSDs or the write data intended to be persistently stored in the one or more NVMe SSDs.

Abstract: Direct memory access (DMA) is provided in a computing system that includes a central processing unit (CPU), CPU memory associated with the CPU, a graphics processing unit (GPU), GPU memory associated with the GPU, a storage device capable of direct memory access, and a peer-to-peer host bus to which the other components are electrically coupled, directly or indirectly. For each page of the GPU physical memory, a data structure representing the page of GPU physical memory is generated, a GPU virtual memory space is allocated, the GPU virtual memory space is mapped to a GPU physical memory space. Based on the data structure representing the page of GPU physical memory, the GPU physical memory space is mapped to a CPU virtual address associated with a user-space process.

Abstract: Direct memory access (DMA) is provided in a computing system that includes a central processing unit (CPU), CPU memory associated with the CPU, a graphics processing unit (GPU), GPU memory associated with the GPU, a storage device capable of direct memory access, and a peer-to-peer host bus to which the other components are electrically coupled, directly or indirectly. For each page of the GPU physical memory, a data structure representing the page of GPU physical memory is generated, a GPU virtual memory space is allocated, the GPU virtual memory space is mapped to a GPU physical memory space. Based on the data structure representing the page of GPU physical memory, the GPU physical memory space is mapped to a CPU virtual address associated with a user-space process.