Abstract: Provided is a wireless communication receiver including an antenna for receiving an RF signal; a first mixer, coupled to the antenna, for performing frequency conversion on the RF signal from the antenna by mixing the RF signal with a local oscillator signal to provide a first intermediate frequency (IF) signal; and a first filter, coupled to the first mixer, configured to pass a predetermined band of frequencies of the first IF signal and to generate a first channel signal. The first filter includes a negative feedback loop coupled to the first mixer for performing negative feedback loop control on the first IF signal; and a positive capacitive feedback loop coupled to the first mixer for performing positive capacitive feedback loop control on the first IF signal, the negative feedback loop and the positive capacitive feedback loop being coupled in parallel.

Abstract: Provided is a wireless communication receiver including an antenna for receiving an RF signal; a first mixer, coupled to the antenna, for performing frequency conversion on the RF signal from the antenna by mixing the RF signal with a local oscillator signal to provide a first intermediate frequency (IF) signal; and a first filter, coupled to the first mixer, configured to pass a predetermined band of frequencies of the first IF signal and to generate a first channel signal. The first filter includes a negative feedback loop coupled to the first mixer for performing negative feedback loop control on the first IF signal; and a positive capacitive feedback loop coupled to the first mixer for performing positive capacitive feedback loop control on the first IF signal, the negative feedback loop and the positive capacitive feedback loop being coupled in parallel.

Abstract: A wireless receiver with high linearity, having an out-band signal bypass filter, a mixer, and a baseband circuit. The out-band signal bypass filter has a first terminal and a second terminal respectively receiving a positive differential signal and a negative differential signal from a former-stage circuit, and the out-band signal bypass filter provides an out-band signal bypass path from the first terminal to the second terminal. The mixer receives a filtered signal from the out-band signal bypass filter. The baseband circuit is coupled to the mixer for generation of an in-phase signal and a quadrature phase signal.

Abstract: A wireless receiver with high linearity, having an out-band signal bypass filter, a mixer, and a baseband circuit. The out-band signal bypass filter has a first terminal and a second terminal respectively receiving a positive differential signal and a negative differential signal from a former-stage circuit, and the out-band signal bypass filter provides an out-band signal bypass path from the first terminal to the second terminal. The mixer receives a filtered signal from the out-band signal bypass filter. The baseband circuit is coupled to the mixer for generation of an in-phase signal and a quadrature phase signal.

Abstract: A sampling circuit for sampling a signal input includes a signal generation circuit, a sampling switch and a control circuit. The signal generation circuit is arranged for generating a first control signal. The sampling switch has a control node, and is arranged for determining a sampling time of the signal input according to a signal level at the control node. The control circuit is arranged for controlling the signal level at the control node, wherein when the signal level at the control node corresponds to a first level, and before a signal level of the first control signal is changed in order to adjust the signal level at the control node to a second level, the control circuit couples the first control signal to the control node.

Abstract: A sampling circuit for sampling a signal input includes a signal generation circuit, a sampling switch and a control circuit. The signal generation circuit is arranged for generating a first control signal. The sampling switch has a control node, and is arranged for determining a sampling time of the signal input according to a signal level at the control node. The control circuit is arranged for controlling the signal level at the control node, wherein when the signal level at the control node corresponds to a first level, and before a signal level of the first control signal is changed in order to adjust the signal level at the control node to a second level, the control circuit couples the first control signal to the control node.

Abstract: A multiplying digital-to-analog converter (MDAC) with capacitive load reset on an operational amplifier and a pipeline analog-to-digital converter using the MDAC are disclosed. The MDAC includes an operational amplifier and first and second switched-capacitor networks sharing the operational amplifier. The operational amplifier is further coupled with first capacitive load cells when the first switched-capacitor network is coupled to the operational amplifier, and the first capacitive load cells are reset when the first switched-capacitor network is disconnected from the operational amplifier. The operational amplifier is further coupled with second capacitive load cells when the second switched-capacitor network is coupled to the operational amplifier, and the second capacitive load cells are reset when the second switched-capacitor network is disconnected from the operational amplifier.

Abstract: A multiplying digital-to-analog converter (MDAC) with capacitive load reset on an operational amplifier and a pipeline analog-to-digital converter using the MDAC are disclosed. The MDAC includes an operational amplifier and first and second switched-capacitor networks sharing the operational amplifier. The operational amplifier is further coupled with first capacitive load cells when the first switched-capacitor network is coupled to the operational amplifier, and the first capacitive load cells are reset when the first switched-capacitor network is disconnected from the operational amplifier. The operational amplifier is further coupled with second capacitive load cells when the second switched-capacitor network is coupled to the operational amplifier, and the second capacitive load cells are reset when the second switched-capacitor network is disconnected from the operational amplifier.

Abstract: A multiplying digital-to-analog converter (MDAC) with high slew rate and a pipeline Analog-to-digital converter using the same. The first set of capacitors for a first input terminal of the operational amplifier (op-amp) includes active capacitors coupling the first input terminal of the op-amp to a first enhanced reference voltage or a common mode terminal in accordance with first digital bits in an amplifying phase of the MDAC, and includes a feedback capacitor coupling the first input terminal of the op-amp to a first output terminal of the op-amp in the amplifying phase. The first set of capacitors contains M capacitor cells. The feedback capacitor between the first set of capacitors contains at most M/(2n) capacitor cells, where n is a number of effective bits provided by a first analog-to-digital converter generating the first digital bits for the active capacitors.

Abstract: A multiplying digital-to-analog converter (MDAC) with high slew rate and a pipeline Analog-to-digital converter using the same. The first set of capacitors for a first input terminal of the operational amplifier (op-amp) includes active capacitors coupling the first input terminal of the op-amp to a first enhanced reference voltage or a common mode terminal in accordance with first digital bits in an amplifying phase of the MDAC, and includes a feedback capacitor coupling the first input terminal of the op-amp to a first output terminal of the op-amp in the amplifying phase. The first set of capacitors contains M capacitor cells. The feedback capacitor between the first set of capacitors contains at most M/(2n) capacitor cells, where n is a number of effective bits provided by a first analog-to-digital converter generating the first digital bits for the active capacitors.

Abstract: A method utilized in an analog-to-digital conversion apparatus, for converting an analog input signal into a digital output signal including a first portion and a second portion, includes: using a comparator circuit to compare the analog input signal with at least one first reference level to generate a preliminary comparison result, the at least one first reference level being used for determining the first portion; estimating the first portion according to the preliminary comparison result; based on the preliminary comparison result, performing the successive approximation procedure to obtain a posterior comparison result according to a plurality of second reference levels, the second reference levels being used for determining the second portion; and, estimating the second portion according to the posterior comparison result. The preliminary and posterior comparison results are generated by the comparator circuit.

Abstract: A method utilized in an analog-to-digital conversion apparatus, for converting an analog input signal into a digital output signal including a first portion and a second portion, includes: using a comparator circuit to compare the analog input signal with at least one first reference level to generate a preliminary comparison result, the at least one first reference level being used for determining the first portion; estimating the first portion according to the preliminary comparison result; based on the preliminary comparison result, performing the successive approximation procedure to obtain a posterior comparison result according to a plurality of second reference levels, the second reference levels being used for determining the second portion; and, estimating the second portion according to the posterior comparison result. The preliminary and posterior comparison results are generated by the comparator circuit.

Abstract: A method utilized in an analog-to-digital conversion apparatus, for converting an analog input signal into a digital output signal including a first portion and a second portion, includes: using a comparator circuit to compare the analog input signal with at least one first reference level to generate a preliminary comparison result, the at least one first reference level being used for determining the first portion; estimating the first portion according to the preliminary comparison result; based on the preliminary comparison result, performing the successive approximation procedure to obtain a posterior comparison result according to a plurality of second reference levels, the second reference levels being used for determining the second portion; and, estimating the second portion according to the posterior comparison result. The preliminary and posterior comparison results are generated by the comparator circuit.