Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a base structure. The semiconductor device structure also includes a first epitaxial structure and a second epitaxial structure sandwiching the channel structures. The semiconductor device structure further includes a gate stack wrapped around each of the channel structures and a backside conductive contact connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. In addition, the semiconductor device structure includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.

Abstract: A micro LED display device includes: a substrate; a plurality of micro light-emitting diodes disposed on the substrate; and a reflective layer and a black layer sequentially stacked on the substrate. The reflective layer and the black layer cover a surface of the substrate, wherein a top surface of the plurality of micro light-emitting diodes is exposed through the reflective layer and the black layer. A plurality of reflective banks and a plurality of black banks are sequentially disposed on the black layer and exposing the plurality of micro light-emitting diodes; and a color-conversion material covers the top surface of at least one of the plurality of micro light-emitting diodes. The color-conversion material is laterally disposed between the plurality of reflective banks. The reflective layer, the black layer, the plurality of reflective banks, and the plurality of black banks overlap each other in a display direction.

Abstract: An impeller includes a hub and a plurality of blades. The blades are arranged around the hub, and each blade includes a leading edge, a blade tip, a root portion, a trailing edge, a windward side and a leeward side. The windward side including a first turning point and a second turning point, a first vertical height difference is formed from the blade tip to the first turning point, and a second vertical height difference is formed from the first turning point to the second turning point, and the first vertical height difference is greater than the second vertical height difference. The impeller apparently reduces the noise.

Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

Abstract: A method includes depositing a first work-function layer and a second work-function layer in a first device region and a second device region, respectively, and depositing a first fluorine-blocking layer and a second fluorine-blocking layer in the first device region and the second device region, respectively. The first fluorine-blocking layer is over the first work-function layer, and the second fluorine-blocking layer is over the second work-function layer. The method further includes removing the second fluorine-blocking layer, and forming a first metal-filling layer over the first fluorine-blocking layer, and a second metal-filling layer over the second work-function layer.

Abstract: A method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer; recessing the portion of the dielectric structure embedded in the ILD layer; after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.

Abstract: A staining kit is provided, including a first pattern including antibodies against T cell, B cell, NK cell, monocyte, regulatory cell, CD8, CD45, and CTLA4; a second pattern including antibodies against T cell, B cell, NK cell, monocyte, regulatory cell, dendritic cell, and CD45; a third pattern including antibodies against T cell, B cell, NK cell, monocyte, CD8, CD45, CD45RA, CD62L, CD197, CX3CR1 and TCR??; and a fourth pattern including antibodies against B cell, CD23, CD38, CD40, CD45 and IgM, wherein the antibodies of each pattern are labeled with fluorescent dyes. A method of identifying characterized immune cell subsets of a disease and a method of predicting the likelihood of NPC in a subject in the need thereof using the staining kit are also provided.

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.

Abstract: A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.

Abstract: A micro LED display device includes: a substrate; a plurality of micro light-emitting diodes disposed on the substrate; and a reflective layer and a black layer sequentially stacked on the substrate. The reflective layer and the black layer cover a surface of the substrate, wherein a top surface of the plurality of micro light-emitting diodes is exposed through the reflective layer and the black layer. A plurality of reflective banks and a plurality of black banks are sequentially disposed on the black layer and exposing the plurality of micro light-emitting diodes; and a color-conversion material covers the top surface of at least one of the plurality of micro light-emitting diodes. The color-conversion material is laterally disposed between the plurality of reflective banks. The reflective layer, the black layer, the plurality of reflective banks, and the plurality of black banks overlap each other in a display direction.

Abstract: A micro light-emitting diode (LED) display panel including a substrate, a first micro LED, a first light-shielding wall, a second micro LED, and a second light-shielding wall is provided. The substrate includes a plurality of pixel regions arranged in an array. The first micro LED is disposed on one of the pixel regions of the substrate. The first light-shielding wall is disposed on the substrate and located beside the first micro LED. The second micro LED is disposed on the one of the pixel regions of the substrate and located beside the first micro LED. The second light-shielding wall is disposed on the substrate and located beside the second micro LED. A light wavelength of the first micro LED is different from a light wavelength of the second micro LED. A height of the first light-shielding wall is smaller than a height of the second light-shielding wall.

Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.

Abstract: A mobile device includes a system circuit board, a metal frame, one or more other antenna elements, a display device, a first feeding element, and an RF (Radio Frequency) module. The system circuit board includes a system ground plane. The metal frame at least includes a first portion and a second portion. The metal frame at least has a first cut point positioned between the first portion and the second portion. The metal frame further has a second cut point for separating the other antenna elements from the first portion. The first cut point is arranged to be close to a middle region of the display device. The first feeding element is directly or indirectly electrically connected to the first portion. A first antenna structure is formed by the first feeding element and the first portion.

Abstract: A micro light-emitting diode display panel includes a substrate, at least one light-emitting element, a reflective layer and a light-absorbing layer. The at least one light-emitting element is disposed on the substrate to define at least one pixel, and each light-emitting element includes micro light-emitting diodes. The reflective layer is disposed on the substrate and located between the micro light-emitting diodes. The reflective layer has cavities surrounding the micro light-emitting diodes, such that a thickness of a portion of the reflective layer close to any one of the micro light-emitting diodes is greater than a thickness of a portion of the reflective layer away from the corresponding micro light-emitting diode. The light-absorbing layer is at least disposed in the cavities of the reflective layer.

Abstract: A micro-light-emitting diode chip includes an epitaxial structure, an electrode, a transparent structure, and a reflection layer. The epitaxial structure has a light exit surface, a back surface opposite to the light exit surface, and a sidewall surface. The sidewall surface is connected to the light exit surface and the back surface. The electrode is electrically coupled to the epitaxial structure. The transparent structure has an inner surface and an outer surface opposite to the inner surface. The inner surface is connected to the sidewall surface. A distance between the outer surface and the inner surface on a plane where the back surface is located is less than a distance between the outer surface and the inner surface on a plane where the light exit surface is located. The reflection layer is in direct contact with the outer surface. A micro-light-emitting diode display is also provided.

Abstract: Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments, and/or combinations and sub-combinations thereof, for dynamic tone mapping of video content. An example embodiment operates by identifying, by a dynamic tone mapping system executing on a media device, characteristics of a first video signal having a first dynamic range based on a frame-by-frame analysis of the first video signal. The example embodiment further operates by modifying, by the dynamic tone mapping system, a tone mapping curve based on the characteristics of the first video signal to generate a modified tone mapping curve. Subsequently, the example embodiment operates by converting, by the dynamic tone mapping system, the first video signal based on the modified tone mapping curve to generate a second video signal having a second dynamic range that is less than the first dynamic range.

Abstract: A device for audio signal processing includes a main processor and two audio processors electrically connected with the main processor. Each audio processor corresponds to a channel of a stereo audio output. The main processor provides an indication signal for the two audio processors. Each audio processor generates a synchronization signal according to the indication signal and performs audio signal processing according to the synchronization signal. The synchronization signals begin simultaneously and have the same frequencies that equal a sampling frequency. Each synchronization signal includes at least one pulse, and a start of each pulse of each synchronization signal is aligned in time with a start of a pulse of the indication signal. The audio signal processing performed by each audio processor begins at an end of one of the at least one pulse in the synchronization signal corresponding to the audio processor.

Abstract: Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments, and/or combinations and sub-combinations thereof, for dynamic tone mapping of video content. An example embodiment operates by identifying, by a dynamic tone mapping system executing on a media device, characteristics of a first video signal having a first dynamic range based on a frame-by-frame analysis of the first video signal. The example embodiment further operates by modifying, by the dynamic tone mapping system, a tone mapping curve based on the characteristics of the first video signal to generate a modified tone mapping curve. Subsequently, the example embodiment operates by converting, by the dynamic tone mapping system, the first video signal based on the modified tone mapping curve to generate a second video signal having a second dynamic range that is less than the first dynamic range.

Abstract: An optical virtual push button touch panel includes a substrate (10), a light emitting member (11), a light guide plate (12), a light permeable plate (13), and a touch control sensing member (14). The substrate is provided with a mounting slot (100). The light emitting member is mounted in the substrate. The light guide plate defines multiple light guide structures (120). The light permeable plate is mounted on the substrate. The touch control sensing member is located between the light permeable plate and the light guide plate and defines multiple contact zones (140) aligning with the light guide structures respectively. One of the contact zones produces a coupling capacitance through the light permeable plate and drives the light emitting member to generate the light source, and one of the light guide structures converges the light source toward one of the contact zones.